PSB2115FV1.2 Infineon Technologies AG, PSB2115FV1.2 Datasheet
PSB2115FV1.2
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PSB2115FV1.2 Summary of contents
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ICs for Communications Smart Integrated Digital Echo Canceller SIDEC PEB 20954 Version 1.1 Preliminary Data Sheet Apr.1999 DS 1 ...
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... Components used in life-support devices or systems must be expressly authorized for such purpose! 1 Critical components of the Infineon Technologies AG, may only be used in life-support devices or systems the express written approval of the Infineon Technologies AG critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system affect its safety or effectiveness of that device or system ...
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Register Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction The Smart Integrated Digital Echo Canceller (SIDEC) suppresses echoes in telecommunication networks which might disturb any kind of terrestrial or wireless communication. It incorporates leading edge CMOS technology as well as SIEMENS’ many years’ experience in Telecommunication ICs. ...
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Smart Integrated Digital Echo Canceller SIDEC Version 1.1 1.1 Key Features • 2.048 MHz PCM input and output interfaces with selectable - and A-Law coding according to ITU G.711 • Rapid convergence of patented algorithm at the beginning or during ...
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Support of Channel Associated Signaling (CAS) BR transparency (robbed bits) in send path • Selectable - to A-Law -Law Conversion on a global or per channel basis • Configurable idle channel supervision • Clear channel capability ...
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Logic Symbol General Pins PORES MODE1 MODE0 Synchronization CLK32SEL CLK32 CTRL32 SCLKI SCLKO SYNCI SYNCO SDECI SDECO RFCLKF RFCLKN RFCLKEX CLK16 CTRL16 RFSPF RFSPN CLK4O SO128 Speech RO128 Highway Interface UPRES Figure 1 Logic Symbol ...
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Typical Applications The SIDEC can be used for various applications. Figure 2 to Figure 5 display typical examples. SDH or PDH FALC PCM30 LH Network PEB 2255 Near End SDH: Synchronous Digital Hierarchy Plesiochronous Digital Hierarchy PDH: ATM: Asynchronous ...
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PSTN POTS Figure 3 SIDEC in a Voice over IP Gateway An emerging market in the telecom industry is “Voice Over IP”. Due to the long delay echo cancellation is required. The delay is introduced through packetizing and voice compression. ...
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POTS SLIC POTS SLIC SLIC SLIC POTS POTS Echo SLIC SLIC POTS POTS PBX: Private Branch eXchange SICOFI: Signal Processing Codec Filter SLIC: Subscriber Line Interface Circuit Figure 4 SIDEC in a Private Branch Exchange (PBX) SIDEC can ...
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POTS POTS Echo POTS E1/T1 SIDEC POTS TRAU: Transcoder Rate Adaptor Unit MSC: Mobile Switching Center Figure 5 SIDEC in a Wireless System Due to voice compression and error correction the one way transmission time for wireless voice signals is ...
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Pin Descriptions 2.1 Pin Diagram NC 109 NC 110 CLK32SEL 111 MODE1 112 MODE0 113 PORES 114 VDD 115 VSS 116 CLK4O 117 SYNCO 118 SCLKO 119 SDECO 120 VDD 121 122 CTRL32 123 VDD 124 VSS 125 CLK32 ...
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Pin Definitions and Functions Table 1 General Pins Pin No. Symbol 114 PORES 112 MODE1 113 MODE0 112 MODE1 113 MODE0 Table 2 Synchronization Pin No. Symbol 111 CLK32SEL 126 CLK32 123 CTRL32 130 SCLKI 119 SCLKO 117 CLK4O ...
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Pin No. Symbol 131 SYNCI 118 SYNCO 120 SDECO 129 SDECI 101 RFCLKF 100 RFCLKN Preliminary Data Sheet I/O, PU/PD Function I, PU System Synchronization input pulse. Defines the frame alignment of PCM and UCCI signals in conjunction with the ...
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Pin No. Symbol 99 RFCLKEX 96 CLK16 106 CTRL16 103 RFSPF 102 RFSPN Preliminary Data Sheet I/O, PU/PD Function I, PU Reference clock (2.048 MHz) for frequency comparison to generate the control voltage for the 16.384 MHz VCXO if Register ...
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Table 3 Microprocessor Interface Pin No. Symbol 78 IM0 77 IM1 71 CS0 70 CS1 46-43 A0..A6 40-38 58-55 AD0..AD7 52-49 67 ALE 69 RD/DS 68 WR/RW 64 INT 61 RDY Preliminary Data Sheet I/O, PU/PD Function I, PU Interface ...
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Table 4 Microcontroller Port Extension Pin No. Symbol 27 UPIO0 28 UPIO1 29 UPIO2 30 UPIO3 Table 5 Processor Watchdog Circuit Pin No. Symbol 63 UPRES 62 UPRES 33 DISWD 34 UPRESI Table 6 Speech Highways Pin No. Symbol 84 ...
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Pin No. Symbol SO128 87 RO128 Preliminary Data Sheet I/O, PU/PD Function O 2.048 Mbit/s Send speech highway output. Start of timeslot 0, bit 7 can be flexibly aligned to the SYNCI/SYNCO pulse in 122 ...
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Table 7 UCC Interface Pin No. Symbol 132 UCCI 135 UCCO 136 TUCCO Table 8 Speech Highway Control Signals for Channel Associated Signaling (CAS Systems Pin No. Symbol 82 TSIGM 81 TMFBI 93 TMFBO Preliminary Data Sheet I/O, ...
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Table 9 Channelwise Serial Interface Pin No. Symbol 12 DIS 11 NLPDIS 10 FREEZE 9 CONVDIS 8 ENCC 7 FLEXSCTR 24 DISMON 23 NLPDISMON 22 FREEZEMON O 21 HRESMON Preliminary Data Sheet I/O, PU/PD Function I, PD Serial 256 kbit/s ...
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Pin No. Symbol 18 FLEXMON1 17 FLEXMON2 16 CONVDISMON O 15 CCMON Preliminary Data Sheet I/O, PU/PD Function O Serial 256 kbit/s monitor output signal (32 channels at 8 kbit/s), monitoring according to settings of the bits CONFLEXMON[7:4], e.g. Idle ...
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Table 10 Test Interface for Boundary Scan according to IEEE 1149.1 Pin No. Symbol 1 TDI 144 TDO 2 TMS 3 TCK 4 TRST Table 11 Test Interface Pin No. Symbol 140 KSCMOD 139 KSCEN 141 TEST Preliminary Data Sheet ...
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Functional Description Figure 7 depicts the Functional Block Diagram of the SIDEC. 3.1 Functional Block Diagram and Description Send In PCM Input Send Path Interface Adaptive Echo Near End Estimation Unit with echo path UCCI Receive Out PCM Output ...
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Section 3.1.3) of the Adaptive Echo Estimation Unit might be necessary. The H-Register reset signal is also provided by the Speech Control. 3.1.2 Disabling Logic Upon request of the Speech Control and depending on external inputs the Disabling ...
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Offset adjustment is implemented at the output of the canceller. The attenuation of 0 dB, 2 programmable by a register. The use of this feature requires that the cancelling function for the corresponding timeslot is ...
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A/ -Law conversion can be operated directly by the hardware without intervention of the microprocessor. This feature reduces the work load of the processor dramatically. 3.1.9 Watchdog Timer A Watchdog timer is ...
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If this modus is chosen by setting CONFLAW.CHIND=’0’ all 32 PCM channels are converted according to the settings of GALAWFE for the far end and GALAWNE for the near end. A ‘1’ in GALAWFE and GALAWNE indicates that A-Law is ...
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Bypass and Disabling Functions Figure 9 depicts the bypass and disabling functions of the SIDEC. They can be configured via UCC, Serial and P Interface. Setting NLPDIS =’1’ (pin or register setting) leads to bypassing of the Non Linear ...
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UCC Interface The UCC Interface uses a clock frequency of 2048 kHz. The UCC Signal is structured into frames (period 125 s) consisting of 32 channels (period 3.9 s) and a multiframe consisting of 32 frames (period 4 ms). ...
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SCLKI SYNCI 125 s frame 3 frame 4 UCCI UCCO frame 3 frame 4 SCLKI SYNCI frame 4, channel 31 UCCI frame 4, channel 31 UCCO TUCCO SCLKI SYNCI frame 3, channel 31 UCCI Bit 0 SMLP* frame 3, channel ...
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Operational Description 4.1 Pin Connection Diagram for SIDEC Figure 11 illustrates an example for the pin connection of the SIDEC to an E1/T1 IC and to an interworking element IC. The SIDEC is used to cancel the echo on ...
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Synchronization and Clock Modes The SIDEC can be connected in different synchronization and clock modes. These modes can be used for several applications. Basically there are two clock modes, slave and master clock mode (not to be mixed up ...
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VCO SCLKI SDECI n.c. Figure 13 Master Clock Mode with External 8.192 MHz Clock In the master clock mode with 8.192 MHz clock (Figure 13), the 32.768 MHz operating clock is supplied by the VCO. The SIDEC provides a controlling ...
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SCLKI SDECI Figure 14 Slave Clock Mode with External 8.192 MHz and 32.768 MHz In the slave clock mode the 8.192 MHz and the 32.768 MHz clock have to be synchronous and phase aligned (e.g. SCLKI has been derived from ...
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VCXO RFCLKF RFCLKN RFCLKEX 2 MHz Figure 15 Reference Clock Mode with 2.048 MHz In this mode a 2.048 MHz system clock is provided at either the RFCLKF, RFCLKN or the RFCLKEX pin. The VCXO and VCO supply the operating ...
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SCLKI SI RO SDECI SCLKI SI Figure 16 128 ms Delay Mode The pin connection of a 128 ms master and slave SIDEC is shown in Figure 16. The SI and RI is supplied to both SIDECs. The RO and ...
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SDECI V DD SCLKI SI RO SDECI SCLKI SI RO Figure 17 Multiple SIDEC In multiple SIDEC mode the output SDECO of the clock master SIDEC is used to synchronize clock slave SIDECs to the system clock. In this application ...
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Timing Patterns 4.3.1 Clock Timing CLK32 1 SDECI SCLKO if CLK32SEL=’1’ CLK16 6 SCLKO if CLK32SEL=’0’ SCLKI 7 CLK4O Figure 18 Clock Timing Table 12 Clock Timing Characteristics (preliminary) No. Name 1 t_clk32_low 2 t_clk32_high 3 t_sdeci_setup 4 t_sdeci_hold ...
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No. Name 6 t_sclko_delay_clk16 SCLKO output delay 7 t_clk4o_delay Table 13 Periods of Clock Signals No. Parameter CLK32 CLK16 SCLKI CLK4O Preliminary Data Sheet Parameter min. 0 after CLK16 CLK4O output delay 0 after SCLKI min PEB 20954 ...
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PCM Signal Timing and Frame Alignment The SIDEC requires the MSB (bit7) first and the LSB (bit0) last as input SCLKI SYNCI (SYNCO) channel 26 RI Bit 2 Bit 1 Bit 0 SI Bit 0 Bit 7 channel 26 ...
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Note: Above values are examples only. PCM frame alignment with respect to the first detection of an active SYNCI (or SYNCO SYNCI is applied, SYNCO takes over the part and role of SYNCI) with the falling edge of ...
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SCLKI SYNCI (SYNCO is only possible if UCC interface is not used) Synchronization for UCC Interface Figure 21 Synchronization of PCM and UCC Signal with respect to SCLKI and SYNCI Table 14 PCM Signal Timing and Frame Characteristics (preliminary) ...
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Timing of SYNCI and SYNCO SYNCI is clocked in with the falling edge and SYNCO is clocked out with the rising edge of SCLKI, SYNCI and SYNCO are active low (CONFCC.SSCLKEDGE = ’0’ and CONFCC.SYNCACT = ’0’) SCLKI SYNCI ...
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Note: The duration CONFCC.SYNCODUR to either one or two SCLKI (8.192 MHz) periods. Table 15 Characteristics of Timing of SYNCI and SYNCO (preliminary) No. Name 1 t_synci_setup 2 t_synci_hold 3 t_synco_delay Preliminary Data Sheet of SYNCO pulse can Parameter SYNCI ...
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Clock Timing within External VCO Capture Range SCLKI Lock-in at 0° CLK32 internal 8Mhz clock CTRL32 Lock-in at 90° CLK32 internal 8Mhz clock CTRL32 Lock-in at 180° CLK32 internal 8Mhz clock CTRL32 Figure 23 Clock Timing within External VCO ...
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Serial Interface (Controlling and Monitoring) Timing CLK32 SCLKO SDECO serial control inputs serial monitor channel 30 outputs CLK32 SCLKO SDECO serial control inputs serial monitor outputs Figure 24 Serial Interface (Controlling and Monitoring) Timing Table 16 Serial Interface (Controlling ...
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No. Name 4 t_smon_delay 5 Preliminary Data Sheet Parameter min. Serial monitor signal 0 output delay after CLK32 SDECO duration 16 * CLK32 period 48 PEB 20954 PEF 20954 Operational Description Limit Values Unit max 04.99 ...
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UCC Interface Signal Timing and Frame Alignment SCLKI SYNCI UCCI ...
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SCLKI can be configured by writing to the registers UCCALIGN and UCCMFR. For finer adjustments, the valid bit phase of the UCC signals at the first detection of an active SYNCI with the falling edge ...
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Special Cases for Multiframe Alignment Case 1: SYNCI at channel 31, bit 0, phase 3 SCLKI SYNCI UCCI/UCCO Phase 1 Bit 0, channel 31, frame 3 Case 2: SYNCI at channel 0, bit 7, phase 0 SCLKI SYNCI Register UCCMFR ...
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Table 17 UCC Interface Signal Timing and Frame Alignment (preliminary) No. Name 1 t_ucci_setup 2 t_ucci_hold 3 t_ucco_delay 4 t_tucco_delay 5 t_ucc_reflect_delay Propagation delay Preliminary Data Sheet Parameter min. UCCI input setup time 15 before sampling with SCLKI UCCI input ...
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Speech Highway Control Signals for CAS in T1 Systems Frame 1 SI TMFBI SYNCI SI 0 TSIGM SO TMFBO Figure 27 Timing of Supporting signals for CAS-BR Applications Preliminary Data Sheet Multiframe n (e.g. F12/SF) Frame 2 Frame 6 ...
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Microprocessor Interface The SIDEC Microprocessor Interface supports both, SIEMENS/Intel and Motorola mode. In each mode the address can be provided either through the multiplexed address/data or a parallel address bus. In multiplexed mode the address is always sampled with ...
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Internal Read Internal Read Condition: SIEMENS/Intel Mode (IM0 = ’0’): Motorola Mode (IM0 = ’1’): Internal Write Internal Read Condition: SIEMENS/Intel Mode (IM0 = ’0’): Motorola Mode (IM0 = ’1’): Figure 28 Internal Read Signal and Internal Write Signal Table ...
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Intel Mode (IM0=’0’) a) Multiplexed Mode (IM1=’0’) ALE 1 AD[7: RDY Figure 29 Read Timing in Multiplexed Intel Mode (IM0=’0’, IM1=’0’) ALE 1 AD[7: RDY Figure 30 Write Timing in Multiplexed Intel Mode (IM0=’0’, IM1=’0’) ...
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Demultiplexed Mode (IM1=’1’) A[5: AD[7:0] RDY Figure 31 Read Timing in Demultiplexed Intel Mode (IM0=’0’, IM1=’1’) A[5: AD[7:0] RDY Figure 32 Write Timing in Demultiplexed Intel Mode (IM0=’0’, IM1=’1’) Preliminary Data Sheet 17a 17b 16a ...
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Motorola Mode (IM0=’1’) a) Multiplexed Mode (IM1=’0’) ALE 1 AD[7: RDY Figure 33 Read Timing in Multiplexed Motorola Mode (IM0=’1’, IM1=’0’) ALE 1 AD[7: RDY Figure 34 Write Timing in Multiplexed Motorola Mode ...
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Demultiplexed Mode (IM1=’1’) A[5: AD[7:0] RW RDY Figure 35 Read Timing in Demultiplexed Motorola Mode (IM0=’1’, IM1=’1’) A[5: AD[7:0] RW RDY Figure 36 Write Timing in Demultiplexed Motorola Mode (IM0=’1’, IM1=’1’) Preliminary Data Sheet 33a ...
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Table 19 Microprocessor Interface Timing for Figure 29 to Figure 36 (preliminary) No. Parameter 1 Address setup before ALE falling edge 2 Address hold after ALE falling edge 3a ALE falling edge before CS active if RD asserted 3b ALE ...
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No. Parameter 11b ALE falling edge before WR rising edge if CS asserted 12a Write data setup before CS rising edge if WR asserted 12b Write data setup before WR rising edge if CS asserted 13a Write data hold after ...
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No. Parameter 20b ALE falling edge before DS active if CS asserted and RW = '1’ 21a RW setup before CS active if DS asserted 21b RW setup before DS active if CS asserted 22a AD output after CS active ...
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No. Parameter 30a Write data hold after CS rising edge if DS asserted and RW = ’0’ 30b Write data hold after DS rising edge if CS asserted and RW = ’0’ 31a CS rising edge before ALE falling edge ...
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JTAG Timing TCK TMS TDI TDO Figure 37 JTAG Boundary Scan Timing Table 20 JTAG Boundary Scan Timing No. Name 1 t_tck_period 2 t_tck_high 3 t_tck_low 4 t_tms_setup 5 t_tms_hold 6 t_tdi_setup 7 t_tdi_hold 8 t_tck_tdo_fall Preliminary Data Sheet ...
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Register Description 5.1 Register Model 5.2 Detailed Register Description In the following section the meaning and addresses of the registers of the SIDEC are described, The addresses and reset values are given in Hex-Code indicated by a subsequent capital ...
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Addr Short Name . 0EH SIALIGN 0FH SOALIGN 10H UCCALIGN 11H PHALIGN 12H CONFSCU1 13H CONFSCU2 14H CONFSCU3 15H CONFSCU4 16H CONFSCU5 17H CONFSCU6 18H CONFSCU7 19H CONFSCU8 1AH CONFSCU9 1BH CONFSCU10 1CH CONFPSD 1DH CONFSS7 1EH MONSIL 1FH MONSOL ...
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Addr Short Name . 28H MONOCDT 29H MONSI 2AH MONSO 2BH MONRI 2CH MONSTAT1 2DH MONSTAT2 2EH MONSTAT3 2FH CTRLTSMON 30H CONFPCM 31H CONFTS16 32H CONFIDLE 33H IDLEMASK 34H IDLEPATTERN 35H ATE 36H SFATSES 37H TESTTIMER 38H CTRLTEST 39H TSGSPP ...
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Addr Short Name . 3DH SOTP 3EH TESTSTAT 3FH CONFLAW 40H CHCTRL0 41H CHCTRL1 42H CHCTRL2 43H CHCTRL3 44H CHCTRL4 45H CHCTRL5 46H CHCTRL6 47H CHCTRL7 48H CHCTRL8 49H CHCTRL9 4AH CHCTRL10 4BH CHCTRL11 4CH CHCTRL12 4DH CHCTRL13 4EH CHCTRL14 ...
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Addr Short Name . 5AH CHCTRL26 5BH CHCTRL27 5CH CHCTRL28 5DH CHCTRL29 5EH CHCTRL30 5FH CHCTRL31 60H CONFUCC 61H UCCMFR 62H UCCFRS 63H WRUCC 64H DORAM 65H IMASKFRS 66H IMASKFRN 67H DIRAM 68H UCCOLD 69H UCCNEW 6AH UCCSTAT 6BH SCMASK ...
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Addr Short Name . 72H AEEPD 73H AVDDI 74H AVDHG 75H AVDCI 76H VDFCTRL 77H ATMAT 78H AACSC 79H ACONF 7AH AFCMC 7BH AFCD1 7CH AFCD2 7DH AFCD3 Preliminary Data Sheet Full name AFI End Echo Path Delay AFI Voice ...
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Read-Write-Register NOTEBOOK[7:0] (Addr.: 00H): Notebook, write protected, Reset value = 00H NOTE NOTE NOTE BOOK[7] BOOK[6] BOOK[5] NOTEBOOK[7:0] Read/Write register for testing of the P interface, content without effect, write protected UPIO[7:0] (Addr.: 05H): P-I/O-Pin extension, Reset value = ...
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RESULT is valid, if the RAMBIST was activated before CUFAIL ’1’: RAMBIST of central unit failed, i.e. a RAM error was detected ’0’: RAMBIST of central unit succesful: no error in RAM AFI3FAIL ’1’: RAMBIST of adaptive filter ...
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WP[7:0] (Addr.: 01H) Write Protection, Reset Value ’protected’= NOT 95H WP[7] WP[6] WP[5] WP[7:0] Write access to the write protected configuration registers is released by writing the value 95H to this register. The write protection is activated by writing any ...
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WDG2[7:0] (Addr.: 03H) Watchdog 2 WDG2[7] WDG2[6] WDG2[5] WDG2[4] WDG2[3] WDG2[2] WDG2[1] WDG2[0] WDG2[7:0] For watchdog test: Must be written with the defined value 99H as the second of the three watchdog registers within 2 seconds WDG3[7:0] (Addr.: 04H) Watchdog ...
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Attenuation of send path output is disabled for all channels SOATTMOD ’1’: Attenuation of send path output is 2 enabled ’0’: Attenuation of send path output enabled ROATTEN ’1’: Attenuation of ...
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CHIND = ’0’ and CONVDIS = ’0’ ’0’: -Law PCM encoding at far end side (RI and SO) if CHIND = ’0’ and CONVDIS = ’0’ *Note: In the case of no A-/ -Law conversion (same law at near ...
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Possible PCM Law conversion is enabled if Bit ENPCTRL = ’1’, Law conversion on/off depends on other hardware sources (serial control signals, UCC) if ENPCTRL = ’0’. FREEZE ’1’: The H-register of the corresponding channel are ...
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SCMASK[5:0] (Addr.: 6BH): Serial Control Interface Mask, write protected, Reset value = 3FH - - DIS MASK This register is for masking of external pins of the Serial Interface. The effect of this register depends also on the value of ...
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No reset of the attenuation meters unit by FLEXSCTR FSHRESET ’1’: serial control signal at pin FLEXSCTR resets the H-Register ’0’: No reset of the H-Register by FLEXSCTR FSCONVDIS ’1’: serial control signal at pin FLEXSCTR disables the PCM-Law ...
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The bits CONFFLEXMON1[3:0] and CONFFLEXMON2[3:0] configure the serial control signals FLEXMON1 and FLEXMON2, respectively. CONFFLEXMON1[3:0] / CONFFLEXMON2[3:0] Configuration of the flexible monitor output signal at pin FLEXMON1/ FLEXMON2 "0000": "0001": "0010": "0011": "0100": "0101": "0110": "0111": "1000": "1001": "1010": "1011": ...
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CONFIDLE[5:0] (Addr.: 32H): Configuration of IDLE Detection, write protected, Reset value = 1DH - - ENIDLE For idle detection the Receive In or Send In input pattern is compared either with itself or with a maskable configurable pattern of ...
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IDLEPATTERN[7:0] (Addr.: 34H): Idlepattern, write protected, Reset value = 55H IDLE IDLE IDLE PAT PAT TERN[7] TERN[6] TERN[5] The reset value corresponds to a level minus infinity for A-Law encoding IDLEPATTERN [7:0] IDLE Pattern for comparison with the receive values ...
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RLISTEN This bit is only active in Reflect Mode which can be configured via bit CONFUCC.RSWCTRL or SMLP bit of UCC Interface. ’1’: UCCI input data will be transferred to IRAM and interrupt will be generated ’0’: Normal operation: No ...
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Note: In 128 ms mode the DIS-Bit and the FX-Bit are only evaluated in the 16 processed channels. UCCMFR[4:0] (Addr.: 61H): UCC Multiframe Alignment, write protected, Reset value = ...
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UCCO and the activation of TUCCO for all frames in 128 ms mode if the number does not correspond to one of the 16 processed channels.* UCCFRS[4:0] Denotes the frame number of ...
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IMASKFRN[7:0] (Addr.: 66H): Interrupt Mask for channel individual UCC frames (FRN), Reset value = 00H IMASK IMASK IMASK FRN[7] FRN[6] FRN[5] IMASKFRN[7:0] Each activated (set to ’1’) mask bit prevents the generation of an UCC interrupt at a change of ...
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TESTTIMER.UPTEST. If the channel that is background tested by the software suddenly becomes enabled by external sources before the test is terminated an interrupt is generated that informs the software to abort ...
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SGMOD1 operation mode1 for signal generator (see Table 21) SPTP [6:0] Send path test pattern amplitude, log, A-/µ-Law encoded TSGRPP[7:0] (Addr.: 3AH): Test signal generator for receive path pattern, Reset value = 55H SG RP MOD0 TP[6] TP[5] SGMOD0 operation ...
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HTIM[7:0] (Addr.: 3BH): High-Byte for Timer, Reset value = 00H TIM[15] TIM[14] TIM[13] The timer can be used by the processor, if the processor wants to do different operations inbetween. The timer is counting downward. The timing decrement is 1 ...
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CONFSCU2[7:0] (Addr.: 13H): Configuration of speech control unit 2, write protected, Reset value = 97H BYP BYP THL[4] THL[3] THL[2] BYPTHL[4:0] Transhybrid loss as of which the canceling unit is bypassed "00000": "00001": "00010": "00011": "00100": "10010": "11111": READD[1:0] Safety ...
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DTTIME[1:0] Double talk hangover time "00" ITUDT ’0’: double talk detection operates transhybrid loss ’1’: double talk detection according ITU: transhybrid loss greater or equal 6 dB CONFSCU4[7:0] (Addr.: 15H): Configuration of speech control ...
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SWMINATT[2:0] Minimum attenuation for switchover to final residual echo level "000" "100" "101": 15dB "110": 18dB "111": 21dB CONFSCU6[7:0] (Addr.: 17H): Configuration of speech control unit 6, write protected, Reset value = 2AH REL REL ADD[2] ...
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CONFSCU8[7:0] (Addr.: 19H), Configuration of speech control unit 8, write protected, Reset value = EEH BNMAX BNMAX BNMAX SL[3] SL[2] SL[1] BNMAXSL[3:0] Maximum send path level for background noise measurement "0000": "0001": "0010": "0011": "0100": ... "1110": ...
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PSNLPDIS ’0’: no disable via 2100 Hz Disabler even with phase shift ’1’: disable via 2100 Hz Disabler with phase shift Coefficient (H-Register) reset: DISHRES ’0’: no reset via 2100 Hz Disabler without phase shift ’1’: reset via 2100 Hz ...
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Increased Speech protection VDFCTRL[7:0] (Addr.: 76H): Voice Detection Freeze Control, write protected, Reset value = B4H VDF VDF VDF RELEN REL[2] REL[1] VDFRELEN ’0’: No freeze of H-Register on no voice detection when combined loss ...
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DBPMIN[1:0] Minimum interruption time that results in response: "00": 1.125 ms "10": 3.375 ms DBPMAX[2:0] Maximum interruption time that results in response: "000" "010" "100" "110" ...
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CONFCC[6:0] (Addr.: 0BH) Configuration of Clock Control unit, write protected, Reset value = 00H - INV SYNC CTRL32 ACT INVCTRL32 ’1’: Inverts the control voltage signal for the 32MHz VCO at pin CTRL32 (see Figure 23) ’0’: no inversion of ...
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FSLIPIV[4:0] Determines the safety interval around the SYNCO pulse, which represents the minimum allowed distance between SYNCO and RFSPN or RFSPF steps. If the distance between RFSPN/F and SYNCO becomes smaller than FSLIPIV[4: SYNCO ...
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UCCALIGN[7:0] (Addr.: 10H): UCC frame alignment,write protected, Reset value = 00H UCC UCC UCC ALIGN[7] ALIGN[6] ALIGN[5] UCCALIGN[7:0] Determines the valid frame bit of the UCC frame (starting with bit 7 channel 0) at the first falling SCLKI edge, with ...
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STFALL[2:0] Saw-tooth falling clock frequency The clock for the increasing a decreasing saw tooth offset voltage is: "000": 4 kHz "010": 1 kHz "100": 250 Hz "110": 62 STRISE[2:0] and STFALL[2:0] are set to "000", the clock will ...
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SIDEC ASICs has to be used in which a single SIDEC chip processes only every other four channels: Master: Slave: If the 128 ms mode is not selected (pins MODE0 and ...
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AVDHG[7:0] (Addr.: 74H): AFI Voice Detection, Hysteresis and Gap, write protected, Reset value = 74H VDSO VDSO VDSO DELAY DELAY DELAY [3] ...
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AVDCI[7:0] (Addr.: 75H): AFI Voice Detection Count Init, write protected, Reset value = 85H VDCI VDCI VDCI [7] [6] VDCI[7:0] Voice Detection Counter Init value: A counter is used to count the number of values within the VDINTERVAL which fulfill ...
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ACSEFFECT ACSEFFECT specifies the effect of slow-down mode. If set to ’1’, coefficient update is limited to increasing/decreasing by at most 1. If set to ’0’, coefficient increment/decrement takes place in the normal way of operation, but turbo mode is ...
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It is configured in the range from -42 dBm0 (VDAT[3:0] = "0001" dBm0 (VDAT[3:0] = "1111") in steps of 3 dBm0. With VDAT set to the default value "0000", no lower limit ...
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Read Register CLKSTAT[5:0] (Addr.: 09H): Clock-Status - - CLKEX RFCLKEX ’1’: no valid 2 MHz clock available at pin RFCLKEX RFCLKN ’1’: no valid 2 MHz clock available at pin RFCLKN RFCLKF ’1’: no valid 2 MHz clock available ...
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UCCPOLL ’1’: UCC status TSMPOLL ’1’: Timeslot monitor status SFATSES[2:0] (Addr.: 36H): Super frame alarm and requested timeslot en/disable status - - TSENVALID ’1’: TSEN value for the requested TS in register ATE is valid ’0’: TSEN value not valid ...
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H-Register not reset ERL ’1’: echo return loss > value of BYPTHL[4:0] ’0’: echo return loss not > value of BYPTHL[4:0] FCM ’1’: fast convergence mode ’0’: normal convergence mode NOSPEECH ’1’: no speech detected ’0’: speech detected DIRAM[7:0] ...
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NOSYNC ’1’: UCC unit is not synchronized to SYNCI pulse, i.e. the SYNCI pulse period is not an integer multiple of 32 UCC frames (4ms). ’0’: UCC unit is synchronized to SYNCI pulse, i.e. a SYNC ...
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AFI Coefficient Register Value ...
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MONSO[7:0] (Addr.: 2AH): Monitor send output signal (A-/µ-Law encoded) MON MON MON SO[7] SO[6] SO[5] The content of this register is PCM encoded. MONRI[7:0] (Addr.: 2BH): Monitor of receive input signal (A-/µ-Law encoded) MON MON MON RI[7] RI[6] RI[5] The ...
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The content of this register is encoded logarithmically. The maximum value of 191 corresponds to 3 dBm0. A decrease equivalent to a decrease of 6 dB. The following table displays the relation between the register value and ...
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MONOFSI[5:0] (Addr.: 21H): Monitor offset in send path input - - MON OFSI[5] The content of this register is a linear value in "1 complement" notation. MONOFSO[5:0] (Addr.: 22H): Monitor offset in send path output - - MON OFSO[5] The ...
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MONCL[7:0] (Addr.: 26H): Monitor combined loss without NLP MON MON MON CL[7] CL[6] CL[5] The content of this register is encoded logarithmically. For conversion to dBm0 see Table 23 . MONNLPTHL[7:0] (Addr.: 27H): Monitor NLP threshold level MON MON MON ...
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MECBP ’1’: Entire echo cancellation path bypassed MONSTAT2[7:0] (Addr.: 2DH): Monitor of internal/external control states ERLBP DT FCM The contents of individual bits of this register can also be output at pin FLEXMON1 or FLEXMON2 if configured ...
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SIDEC Performance This section describes the preliminary performance of the SIDEC. The measurements are based on the preliminary emulation results. The test, signals and methods are described in ITU G.168. For the measurements a regular analog hybrid with 6 ...
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Figure 40 SIDEC steady state behavior with NLP disabled Preliminary Data Sheet -20 -10 L (dBm0) Rin 117 PEB 20954 PEF 20954 SIDEC Performance ITU requirement SIDEC 0 04.99 ...
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Test No Convergence and steady state residual and returned echo level test 6.2.1 Test 2A: Convergence test with NLP enabled Receive Level R Requirement in ITU G.168 0 dBm0 < -10 dBm0 < ...
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Test No Performance under conditions of double talk 6.3.1 Test 3A: Double talk test with low near end levels For this test the NLP is disabled and the convergence time is t Receive Level ...
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Infinite return loss convergence test The previous echo return loss analog hybrid. The NLP is disabled and the measurement is made 500 ms after interrupting the end echo path. Receive Level ...
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Test No Comfort noise test The SIDEC is fitted with a circuit which is in compliance with this requirement, but most subscribers prefer the solution which limit the send in signal (noise from the near end + ...
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Electrical Characteristics 7.1 Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature IC supply voltage Voltage on any functional pin (not V not ) with respect to ground SS 1) ESD robustness HBM: 1 100 pF ...
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DC Characteristics Parameter Input low voltage Input high voltage Output low voltage Output high voltage Avg. power supply current Input leakage current Output leakage current 1) Permanent exposure to negative input voltages may result in minor degradation of lifetime ...
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Parameter Output low voltage Output high voltage 1) Permanent exposure to negative input voltages may result in minor degradation of lifetime 2) Apply to the following O or I/O pins: UPIO0, UPIO1, UPIO2, UPIO3, AD[0:6], RDY, UPRES, UPRES, INT, RO, ...
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Package Outlines TQFP-144 (144pin Thin Plastic Quad Flatpack 0.5 17.5 +0.05 0.22 0. 144x 144 1 Index Marking 1) Does not include plastic or metal protrusion of 0.25 ...
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Glossary acoustic echo Acoustic echoes consist of reflected signals caused by acoustic environments, e.g. hands-free phones which are connected with a 2-wire circuit to a hybrid. An echo path is introduced by the acoustic path from earphone to microphone. ...
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Network Elements Near-end Hybrid Network Elements Figure 42 Location of levels and loss of an echo canceller echo path The transmission path between R to describe the signal path of the echo. echo path capacity The maximum echo path ...
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The attenuation of the echo signal as it passes through the send path of an echo canceller. This definition specifically excludes any non-linear processing on the output of the canceller to provide for further ...
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NOTE 2 – An example of a NLP is an analogue center clipper in which all signal levels below a defined threshold are forced to some minimum value. non-linear processing loss (A Additional attenuation of residual echo level by a ...
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RET RIN ECHO CANC If non-linear processing is not present, note that L Preliminary Data Sheet + A ) NLP = L RES 130 PEB 20954 PEF 20954 Glossary . RET 04.99 ...
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Index A Adaptive Echo Estimation B background noise 6, 93, 118 Boundary Scan 7 C Channel Associated Signaling Clock 27, 33, 39, 40, 124 combined loss 114 comfort noise 6, 92 continuity check 6, 96, 120 D Disabling 29 ...
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N Non Linear Processor 25, 26, 91 overcompensation 91 P PCM 41, 42, 50, 74 PCM Input/Output Interface R RAM BIST 27 Serial Interface 6, 21, 47, 78 Speech Control 24, 26 Subtractor 25, 26, 93 ...