SAB-C508-4EM Infineon Technologies AG, SAB-C508-4EM Datasheet
SAB-C508-4EM
Available stocks
Related parts for SAB-C508-4EM
SAB-C508-4EM Summary of contents
Page 1
...
Page 2
... Edition 2000-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2000. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
Page 3
C508 ...
Page 4
C508 Revision History: Previous Version: Page Subjects (major changes since last revision) several Typo errors corrected 27 Figure 10 corrected Enhanced Hooks Technology licensed to Infineon Technologies. We Listen to Your Comments Any information within this document that you feel ...
Page 5
CMOS Microcontroller C500 Family C508 • Fully compatible to standard 8051 microcontroller • Superset of the 8051 architecture with 8 datapointers • MHz internal CPU clock (using built-in PLL with a factor of 2) – external ...
Page 6
... For the available ordering codes for the C508, please refer to the “Product Information Microcontrollers” which summarizes all available microcontroller variants. Note: The ordering codes for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Data Sheet SAB-C508 = SAF-C508 = – ...
Page 7
V DDA V SSA V AREF V AGND XTAL1 XTAL2 RESET EA ALE PSEN Figure 2 Logic Symbol Data Sheet Port 0 8-Bit Digital I/O Port 1 8-Bit Digital I/O Port 2 8-Bit Digital I/O C508 ...
Page 8
P2.5/A13 49 P2.4/A12 50 P2.3/A11 51 P2.2/A10 52 P2.1/A9 53 P2.0/ P0.0/AD0 57 P0.1/AD1 58 P0.2/AD2 59 ...
Page 9
P5.3/T2CC3/INT6 P5.2/T2CC2/INT5 P5.1/T2CC1/INT4 P5.0/T2CC0/INT3 Figure 4 Pin Configuration for P-SDIP-64-2 Package (top view) Data Sheet P0.0/AD0 1 P0.1/AD1 2 P0.2/AD2 3 P0.3/AD3 4 P0.4/AD4 5 P0.5/AD5 6 P0.6/AD6 7 P0.7/AD7 8 RESET DDA V 12 ...
Page 10
Table 1 Pin Defintions and Functions Sym- Pin Numbers bol P-MQFP-64 P-SDIP-64 P1. P1 Data Sheet 1) I/O ...
Page 11
Table 1 Pin Defintions and Functions (cont’d) Sym- Pin Numbers bol P-MQFP-64 P-SDIP-64 RESET 1 9 P3. P3 ...
Page 12
Table 1 Pin Defintions and Functions (cont’d) Sym- Pin Numbers bol P-MQFP-64 P-SDIP-64 P2. P2.7 XTAL1 42 50 XTAL2 41 49 Data Sheet 1) I/O Function I/O Port 8-bit quasi-bidirectional I/O ...
Page 13
... It is activated every one and a half oscillator periods except during an external data memory access. When instructions are executed from internal ROM ( the ALE generation can be disabled by bit EALE in SFR SYSCON. This pin should not be driven during reset operation. I External Access Enable ...
Page 14
Table 1 Pin Defintions and Functions (cont’d) Sym- Pin Numbers bol P-MQFP-64 P-SDIP-64 P0. P0.7 P5. P5.7 Data Sheet 1) I/O Function I/O Port 8-bit ...
Page 15
Table 1 Pin Defintions and Functions (cont’d) Sym- Pin Numbers bol P-MQFP-64 P-SDIP-64 V 24, 43, 55 32, 51, 63 – 23, 44, 56 31, 52, 64 – DDA SSA V ...
Page 16
C508 V DD Oscillator V SS Watchdog XTAL1 OSC & Timing PLL, factor of 2 XTAL2 RESET CPU 8 Datapointers ALE PSEN Programmable Watchdog Timer EA Timer 0 Timer 1 Timer 2 with 4 PWM Channels USART Baudrate generator Capture/Compare ...
Page 17
CPU The C508 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting ...
Page 18
Memory Organization The C508 CPU manipulates operands in the following five address spaces: • Kbytes of program memory: • Kbytes of external data memory • 256 bytes of internal data memory • 1024 bytes ...
Page 19
Reset and System Clock Operation The reset input is an active high input. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (6 oscillator periods) while the oscillator is running. ...
Page 20
Figure 8 shows the recommended oscillator circuitries for crystal and external clock operation. Crystal Oscillator Mode C 5-10 MHz for crystal operation (incl. Stray Capacitance) Figure 8 Recommended Oscillator Circuitries Data Sheet ...
Page 21
Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of ...
Page 22
... The 81 special function registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits 0-2 are 0 (e. … are bit-addressable. The SFRs of the C508 are listed Table 3. In ...
Page 23
Table 2 Special Function Registers - Functional Blocks Block Symbol Name CPU ACC Accumulator B B-Register DPH Data Pointer, High Byte DPL Data Pointer, Low Byte DPSEL Data Pointer Select Register PSW Program Status Word Register SP Stack Pointer 4) ...
Page 24
Table 2 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Timer 0/ TCON Timer 0/1 Control Register Timer 1 TH0 Timer 0, High Byte TH1 Timer 1, High Byte TL0 Timer 0, Low Byte TL1 Timer 1, Low ...
Page 25
... Modes 1) This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 2) Bit-addressable special function registers 3) The content of this SFR varies with the actual step of the C508 (e. This special function register is listed repeatedly since some bits of it also belong to other functional blocks. ...
Page 26
Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses Addr. Register Content after 1) Reset DPL DPH ...
Page 27
Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr. Register Content after 1) Reset SYSCON XX10- H XX01 IEN1 X000- H 0000 B B9 ...
Page 28
Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr. Register Content after 1) Reset D2 CP2L CP2H XXXX. H XX00 B D4 CMP2L CMP2H XXXX. H ...
Page 29
... “X” means that the value is undefined and the location is reserved. 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) These are read-only registers. 5) The content of this SFR varies with the actual step of the C508 (e.g. 01 C508-4R, first step) ...
Page 30
Otherwise, the Port 2 pins continue emitting the P2 SFR contents. In this function, Port 0 is not an open-drain port, but uses a ...
Page 31
Timer/Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 5 Timer/Counter 0 and 1 Operating Modes Mode Description 0 8-bit timer/counter with a divide-by-32 prescaler 0 1 16-bit timer/counter 2 ...
Page 32
Timer/Counter 2 with Additional Compare/Capture/Reload Timer 2 with additional compare/capture/reload features is one of the most powerful peripheral units of the C508. It can be used for all kinds of digital signal generation and event capturing like pulse generation, pulse ...
Page 33
Timer 2 Operation Timer 2, which is a 16-bit-wide register, operates as a timer with its count rate derived from the oscillator frequency. A prescaler offers the possibility of selecting a count rate of 1/3 or 1/6 of the oscillator ...
Page 34
Compare Register Circuit Compare Reg. 16-Bit Comparator Compare Match 16-Bit Timer Register Timer Timer Circuit Overflow Figure 12 Port Latch in Compare Mode 0 Compare Mode 1 In compare mode 1, the software adaptively determines the transition of the output ...
Page 35
Compare Register Circuit Compare Reg. 16-Bit Comparator Compare Match 16-Bit Timer Register Timer Circuit Figure 13 Port Latch in Compare Mode 1 Capture Function Two different modes are provided for this function. In mode 0, an external event latches the ...
Page 36
Capture/Compare Unit (CCU) The Capture/Compare Unit (CCU) of the C508 has been designed for applications which demand for digital signal generation and/or event capturing (e.g. pulse width modulation, pulse width measuring). It consists of a 16-bit three-channel capture/compare unit (CAPCOM) ...
Page 37
Capture/Compare Unit (CAPCOM) Period Register (CCPH, CCPL) Offset Register (CT1OFH,CT1OFL OSC Compare Timer 1 (16-Bit) Cntrl. Register (CT1CON) 10-Bit Compare Unit (COMP) Period Register (CP2H, CP2L) Compare 2 f OSC Timer 2 (10-Bit) Cntrl. Register (CT2CON) Figure ...
Page 38
Compare Timer 1 Operating Mode 0 a) Standard PWM (Edge Aligned) Period Value Compare Value 0000 H CCx COUTx Compare Timer 1 Operating Mode 1 c) Symmetrical PWM (Center Aligned) Period Value Compare Value 0000 H CCx COINI=0 COUTx COINI=1 ...
Page 39
... Compare Timer 2 period match event CAPCOM compare match or capture event, and at a CAPCOM emergency event. An emergency event occurs if an active CTRAP signal is detected error condition in block commutation mode is detected. All interrupt sources can be enabled/disabled individually. Table 6 Resolution and Period of the Compare Timer 1 (at ...
Page 40
Compare (COMP) Unit Operation The Capture/Compare Unit CCU of the C508 also provides a 10-bit Compare Unit (COMP) which operates as a single channel pulse generator with a pulse width modulated output signal. This output signal is available at the ...
Page 41
In the combined multi-channel PWM modes the signal generation of the CCx and COUTx PWM outputs can basically be controlled either by the interrupt inputs INT0 to INT2 (block commutation mode the operation of Compare Timer 1 or ...
Page 42
Block Commutation PWM Mode In block commutation mode the INT0-2 inputs are sampled once each processor cycle. If the input signal combination at INT0-2 changes its state, the outputs CCx and COUTx are set to their new state according to ...
Page 43
Serial Interface The serial port of the C508 is full duplex, meaning it can transmit and receive simultaneously also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from ...
Page 44
Baud Rate Generation There are several possibilities to generate the baud rate clock for the serial port depending on the mode in which it is operating. Timer 1 Overflow Baudrate Generator f 2 (SRELH OSC SRELL) 6 Note: The switch ...
Page 45
Table 9 below lists the values/formulas for the baud rate calculations of the serial interface with its dependencies of the control bits BD and SMOD. Table 9 Serial Interface - Baud Rate Dependencies Serial Interface Active Control Bits Baud Rate ...
Page 46
A/D Converter The C508 provides an A/D converter with the following features: • 8 input channels (Port 4) which can also be used as digital inputs • 10-bit resolution • Single or continuous conversion mode • Interrupt request generation ...
Page 47
IEN1 ( SWDT IRCON ( TF2 P4 ( P4.7 P4.6 ADCON1 (DC ADCL1 ADCL0 ADCON0 (D8 BD CLK Port 4 MUX f Clock 2 OSC Prescaler ÷ 32, 16 AREF ...
Page 48
Interrupt System The C508 provides nineteen interrupt vectors with four priority levels. Nine interrupt requests are generated by the on-chip peripherals (Timer 0, Timer 1, Timer 2, Serial Channel, A/D Converter, and the Capture/Compare Unit with four interrupts) and ten ...
Page 49
... P3.2/ INT0 IT0 TCON.0 A/D Converter Timer 0 Overflow P5.4/ INT2 I2FR T2CON.5 Bit Addressable Request flag is cleared by hardware Figure 21 Interrupt Structure, Overview Part 1 Data Sheet IE0 0003 H TCON.1 EX0 IEN0.0 IADC 0043 H IRCON.0 EADC IEN1.0 TF0 000B H TCON.5 ET0 IEN0.1 IEX2 004B H IRCON.1 EX2 IEN1 ...
Page 50
... TRCON.6 ETRP CCU CT1CON.6 Emergency Interrupt BCERR BCON.3 EBCE BCON.4 P5.0/ T2CC0/ INT3 I3FR T2CON.6 P5.7/ INT7 I7FR EINT.0 Bit Addressable Request flag is cleared by hardware Figure 22 Interrupt Structure, Overview Part 2 Data Sheet IE1 0013 H TCON.3 EX1 IEN0.2 1 0093 H ECEM IEN2.2 IEX3 0053 H IRCON.2 EX3 IEN1 ...
Page 51
... Timer 1 TF1 Overflow TCON.7 Compare Timer 2 CT2P Interrupt CT2CON.7 P5.1/ T2CC1/ IEX4 INT4 IRCON.3 P5.6/ INT8 I8FR EINT.2 Bit Addressable Request flag is cleared by hardware Figure 23 Interrupt Structure, Overview Part 3 Data Sheet 001B H ET1 IEN0.3 009B H ECT2 IEN2.3 005B H EX4 IEN1.3 IEX8 00DB H EINT.3 EX8 IEN3 ...
Page 52
... CCIE0.3 CC2R CC2REN P1.6/ CCIR.4 CCIE0.4 CC2 CC2F CC2FEN CCIR.5 CCIE0.5 Capture/Compare Match Interrupt P5.2/ T2CC2/ INT5 P5.5/ INT9 I9FR EINT.4 Bit Addressable Request flag is cleared by hardware Figure 24 Interrupt Structure, Overview Part 4 Data Sheet 1 0023 H ES IEN0.4 1 00A3 ECCM H IEN2.4 IEX5 0063 H IRCON.4 EX5 IEN1 ...
Page 53
... TF2 Overflow IRCON.6 CT1FP CCIR.7 ECTP Compare CCIE.7 Timer 1 Interrupt CT1FC CCIR.6 ECTC CCIE.6 P5.3/ T2CC3/ IEX6 INT6 IRCON.5 Bit Addressable Request flag is cleared by hardware Figure 25 Interrupt Structure, Overview Part 5 Data Sheet 002B H ET2 IEN0.5 1 00AB H ECT1 IEN2.5 006B H EX6 IEN1.5 EA IP1.5 IEN0 ...
Page 54
Table 10 Interrupt Source and Vectors Interrupt Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Channel Timer 2 Overflow A/D Converter External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External ...
Page 55
Fail Save Mechanisms The C508 offers enhanced fail save mechanisms, which allow an automatic recovery from software or hardware failure: – a programmable watchdog timer (WDT), with variable time-out period from 153 314.573 OSC – ...
Page 56
The Watchdog Timer can be started by software (bit SWDT in SFR IEN1), but it cannot be stopped during active mode of the device. If the software fails to clear the Watchdog Timer an internal reset will be initiated. The ...
Page 57
... Functional Block Diagram of the Oscillator Watchdog Fast Internal Reset after Power-On Normally the members of the 8051 family (e.g. SAB 80C52) do not enter their default reset state before the on-chip oscillator starts. In the C508, after power-on, the Oscillator Watchdog’s RC oscillator starts working within a very short start-up time (typ. less than 2 s). The watchdog circuitry detects a failure condition for the on-chip oscillator because they have not yet started (a failure is always recognized if the watchdog’ ...
Page 58
Power Saving Modes The C508 provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and ...
Page 59
State of Pins in Software Initiated Power Saving Modes In the idle mode and power down mode, the port pins of the C508 have well defined states which is listed in the following the location of the code memory (internal ...
Page 60
... ORL PCON1,#90 (to wake-up via pin P5.7/INT7) ANL SYSCON,#0EF ORL PCON,#02 H ORL PCON,#40 H With external wake-up capability from power down disabled ORL PCON,#02 H ORL PCON,#40 H Data Sheet Leaving by Occurance of any enabled interrupt Hardware Reset ANL PCON,#0EF ...
Page 61
OTP Memory Operation (C508-4E only) The C508-4E is the OTP version of the C508 microcontroller with a 32K byte one-time programmable (OTP) program memory. Fast programming cycles are achieved (1 byte in 100 s) with the C508-4E. Several levels of ...
Page 62
Pin Configuration in Programming Mode A5/A13 49 A4/A12 50 A3/A11 51 A2/A10 52 A1/A9 53 A0/ Figure ...
Page 63
Figure 30 OTP Programming Mode Pin Configuration for P-SDIP-64-2 Package (top view) Data Sheet RESET 9 ...
Page 64
Pin Definitions Table 14 contains the functional description of all C508-4E pins which are required for OTP memory programming. Table 14 Pin Definitions and Functions of the C508-4E in Programming Mode Symbol Pin Number P-MQFP-64-1 P-SDIP-64-2 RESET 1 9 PMSEL0 ...
Page 65
Table 14 Pin Definitions and Functions of the C508-4E in Programming Mode (cont’d) Symbol Pin Number P-MQFP-64-1 P-SDIP-64-2 XTAL1 24, 43, 55 32, 51 23, 44, 56 31, 52 P2. ...
Page 66
Programming Mode Selection The selection for the OTP programming mode can be separated into two different parts: – Basic programming mode selection – Access mode selection With basic programming mode selection, the device is put into the mode in which ...
Page 67
Table 15 Access Modes Selection Access Mode Program OTP memory byte Read OTP memory byte Program OTP lock bits Read OTP lock bits Read OTP version byte Data Sheet EA/ PROG PRD PMSEL ...
Page 68
... Note: A ‘1’ means that the lock bit is unprogrammed, a ‘0’ means that lock bit is programmed. Data Sheet Protection Type The OTP lock feature is disabled. During normal operation of the C508-4E, the state of the EA pin is not latched on reset. During normal operation of the C508-4E, MOVC ...
Page 69
... V on pins with respect to ground ( DD the absolute maximum ratings. Operating Conditions Parameter Supply voltage Ground voltage Ambient temperature SAB-C508 SAF-C508 Analog reference voltage Analog ground voltage Analog input voltage CPU clock Data Sheet Symbol Limit Values min. T – ...
Page 70
Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C508 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column ...
Page 71
DC Characteristics (cont’d) (Operating Conditions apply) Parameter Symbol V Output high voltage (Port 0 in external bus mode, ALE, PSEN) Logic 0 input current I IL (Ports Logical 0-to-1 TL transition current (Ports 1, 2, ...
Page 72
Power Supply Current Parameter Active mode C508-4E 5 MHz C508-4R 5 MHz Idle mode C508-4E 5 MHz C508-4R 5 MHz Active mode with C508-4E 5 MHz slow-down enabled C508-4R 5 MHz Idle mode with C508-4E 5 MHz slow-down enabled C508-4R ...
Page 73
... DD XTAL1 driven with ns Port RESET = DD oscillator is used (approx (idle mode) is measured with all output pins disconnected and with all peripherals disabled; DD XTAL1 driven with ns RESET = Port0 = (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals DD disabled ...
Page 74
Figure 32 Diagram DD Data Sheet 50 C508- DDmax 40 I DDtyp 30 Active Mode 20 Idle Mode Active + Slow Down Mode 10 Idle + Slow Down Mode ...
Page 75
Power Supply Current Calculation Formulas Parameter Active mode Idle mode Active mode with slow-down enabled Idle mode with slow-down enabled Data Sheet Symbol C508- typ I DD max I C508-4R DD typ I DD max I C508-4E DD ...
Page 76
A/D Converter Characteristics (Operating conditions apply) Parameter Symbol V Analog input voltage t Sample time S t Conversion cycle time ADCC Total unadjusted error TUE Internal resistance of R reference voltage source Internal resistance of R analog source ADC input ...
Page 77
Notes may exceed V or AIN AGND these cases will During the sample time the input capacitance internal resistance of the analog source must allow the capacitance to reach their final voltage ...
Page 78
Definition of Internal Timing The internal operation of the C508 is controlled by the internal CPU clock derived from the oscillator clock. The high time and the low time of the CPU clock at 50% duty cycle is referred to ...
Page 79
AC Characteristics (Operating conditions apply for Port 0, ALE and PSEN outputs = 100 pF; L Parameter Program Memory Characteristics ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE ...
Page 80
AC Characteristics (cont’d) (Operating conditions apply for Port 0, ALE and PSEN outputs = 100 pF; L Parameter External Data Memory Characteristics RD pulse width WR pulse width Address hold after ALE RD to valid data in Data ...
Page 81
External Clock Drive Characteristics Parameter Oscillator period High time Low time Rise time Fall time ALE PSEN Port 0 Port 2 Figure 34 Program Memory Read Cycle Data Sheet Symbol Freq MHz to 10 MHz min ...
Page 82
ALE PSEN RD t AVLL from Port DPL t AVWL Port 2 Figure 35 Data Memory Read Cycle Data Sheet t LLDV t t LLWL RLRH t RLDV LLAX2 t RLAZ Data IN ...
Page 83
ALE PSEN WR t AVLL from Port DPL t AVWL Port 2 Figure 36 Data Memory Write Cycle t 1 Figure 37 External Clock Drive on XTAL1 Data Sheet t t LLWL WLWH ...
Page 84
AC Characteristics of Programming Mode (Operating conditions apply) Parameter PALE pulse width PMSEL setup to PALE rising edge Address setup to PALE, PROG, or PRD falling edge Address hold after PALE, PROG, or PRD falling edge Address, data setup to ...
Page 85
PAW PALE t PMS PMSEL1,0 t PAS A8-A13 Port 2 Port 0 PROG Note: PRD must be held high during a programming write cycle. Figure 38 Programming Code Byte - Write Cycle Timing Data Sheet PAH ...
Page 86
PAW PALE t PMS PMSEL1,0 t Port 2 Port 0 PRD Note: PROG must be high during a programming read cycle. Figure 39 Verify Code Byte - Read Cycle Timing Data Sheet PAS PAH A8-A13 t ...
Page 87
PMSEL1,0 Port 0 t PMS PROG PRD Note: PALE should be low during a lock bit read/write cycle. Figure 40 Lock Bit Access Timing PMSEL1,0 Port 2 Port 0 PRD Note: PROG must be high during a programming read cycle. ...
Page 88
ROM/OTP Verification Characteristics for C508-4R/C508-4E ROM Verification Mode 1 (C508-4R only) Parameter Address to valid data P1.0-P1.7 P2.0-P2.6 Port 0 Address: P1 P2 A14 Data: P0.0 - P0.7 = ...
Page 89
ROM/OTP Verification Mode 2 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency ALE Port 0 P3.5 Figure 43 ROM Verification Mode 0.5 DD 0.45 ...
Page 90
V +0.1 V Load V Load V Load For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V ...
Page 91
Package Information P-MQFP-64-1 (SMD) (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet 87 C508 Dimensions in mm 2000-08 ...
Page 92
P-SDIP-64-2 (SMD) (Plastic Shrink Dual In-Line Package) 1.78 1 ±0 Index Marking 1) Does not include plastic or metal protrusions of 0.25 max per side Sorts of Packing Package outlines for tubes, trays etc. are contained in our ...
Page 93
... Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.” Dr. Ulrich Schumacher Published by Infineon Technologies AG ...