AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 655

• Manufacturer Part Number: AT32UC3A364
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A364

• Flash (kbytes): 64 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32072G–11/2011
•Single-block transfer programming example for OUT transfer :
•Programming example for single-block dma transfer with automatic closure for OUT transfer :
The following sequence may be used:
The UDDMAnSTATUS.CHEN bit is set indicating that the dma channel is enable.
As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit
is set to one, indicating that the DMA channel is transfering data from the endpoint to the desti-
nation address until the endpoint is empty or the channel byte length is reached. Once the
endpoint is empty, the UDDMAnSTATUS.CHACTIVE bit is cleared.
Once the DMA channel is completed (i.e : the channel byte length is reached), after one or mul-
tiple processed OUT packet, the UDDMAnCONTROL.CHEN bit is cleared. As a consequence,
the UDDMAnSTATUS.CHEN bit is also cleared, and the UDDMAnSTATUS.EOCHBUFFSTA bit
is set indicating a end of dma channel. If the UDDMAnCONTROL.DMAENDEN bit was set, the
last endpoint bank will be properly released even if there are some residual datas inside, i.e:
OUT packet truncation at the end of DMA buffer when the dma channel byte lenght is not an
integral multiple of the endpoint size.
The idea is to automatically close the DMA transfer at the end of the OUT transaction (received
short packet). The following sequence may be used:
As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit
is set to one, indicating that the DMA channel is transfering data from the endpoint to the desti-
n a t i o n a d d r e s s u n t i l t h e e n d p o i n t i s e m p t y . O n c e t h e e n d p o i n t i s e m p t y , t h e
UDDMAnSTATUS.CHACTIVE bit is cleared.
After one or multiple processed OUT packet, the DMA channel is completed after sourcing a
short packet. Then, the UDDMAnCONTROL.CHEN bit is cleared. As a consequence, after a few
cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared, and the UDDMAnSTA-
TUS.EOTSTA bit is set indicating that the DMA was closed by a end of USB transaction.
• Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching
• Write the starting destination address in the UDDMAnADDR register.
• There is no need to program the UDDMAnNEXTDESC register.
• Program the channel byte length in the UDDMAnCONTROL register.
• Program the UDDMAnCONTROL according to Row 2 as shown in
• Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching
• Write the starting destination address in the UDDMAnADDR register.
• There is no need to program the UDDMAnNEXTDESC register.
• Program the channel byte length in the UDDMAnCONTROL register.
• Set the BUFFCLOSEINEN bit in the UDDMAnCONTROL register.
• Program the UDDMAnCONTROL according to Row 2 as shown in
for this endpoint in the UECFGn register to handle multiple OUT packet.
to set up a single block transfer.
for this endpoint in the UECFGn register to handle multiple OUT packet.
to set up a single block transfer.
Figure 26-6 on page 707
Figure 26-6 on page 707
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