AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 71

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AT32UC3A364

Manufacturer Part Number
AT32UC3A364
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3A364

Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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7.6.13
Name:
Access Type:
Offset:
Reset Value:
• DIV: Division Factor
• DIVEN: Divide Enable
• CEN: Clock Enable
• PLLSEL: PLL Select
• OSCSEL: Oscillator Select
32072G–11/2011
31
23
15
7
-
-
-
There is one GCCTRL register per generic clock in the design.
0: The generic clock equals the undivided source clock.
1: The generic clock equals the source clock divided by 2*(DIV+1).
0: Clock is stopped.
1: Clock is running.
0: Oscillator is source for the generic clock.
1: PLL is source for the generic clock.
0: Oscillator (or PLL) 0 is source for the generic clock.
1: Oscillator (or PLL) 1 is source for the generic clock.
Generic Clock Control Register
30
22
14
GCCTRLx
Read/Write
0x60 - 0x74
0x00000000
6
-
-
-
29
21
13
5
-
-
-
DIVEN
28
20
12
4
-
-
DIV[7:0]
27
19
11
3
-
-
-
CEN
26
18
10
2
-
-
PLLSEL
25
17
9
1
-
-
OSCSEL
24
16
8
0
-
-
71

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