AT89LP51RD2 Atmel Corporation, AT89LP51RD2 Datasheet
AT89LP51RD2
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AT89LP51RD2 Summary of contents
Page 1
... Quasi-bidirectional (80C51 Style), Input-only (Tristate) • Push-pull CMOS Output, Open-drain • Operating Conditions – 2.4V to 5.5V V Voltage Range CC – -40° 85°C Temperature Range – MHz @ 2.4V–5.5V (Single-cycle) 8-bit Flash Microcontroller with 64K bytes Program Memory AT89LP51RD2 AT89LP51ED2 AT89LP51ID2 Preliminary 3714A–MICRO–7/11 ...
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... Pin Configurations 1.1 44-lead TQFP/LQFP (†MOSI/CEX2/MISO) P1.5 (†MISO/CEX3/SCK) P1.6 (†SCK/CEX4/MOSI) P1.7 † SPI in remap mode ‡ AT89LP51ID2 Only 1.2 44-lead PLCC (†MOSI/CEX2/MISO) P1.5 (†MISO/CEX3/SCK) P1.6 (†SCK/CEX4/MOSI) P1.7 † SPI in remap mode ‡ AT89LP51ID2 Only AT89LP51RD2/ED2/ID2 Preliminary (DCL) RST 4 (RXD) P3.0 5 (SDA) P4.1 6 (TXD) P3.1 7 (INT0) P3.2 8 (INT1) P3.3 9 (T0) P3.4 10 (T1) P3 (DCL) RST 10 (RXD) P3 ...
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... VQFN/QFN/MLF † SPI in remap mode ‡ AT89LP51ID2 Only (†MOSI/CEX2/MISO) P1.5 (†MISO/CEX3/SCK) P1.6 (†SCK/CEX4/MOSI) P1.7 1.4 40-pin PDIP Note: 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary (DCL) RST 4 (RXD) P3.0 5 (SDA) P4.1 6 (TXD) P3.1 7 (INT0) P3.2 8 (INT1) P3.3 9 (T0) P3.4 10 (T1) P3.5 11 NOTE: Bottom pad should be soldered to ground (T2) P1.0 1 (SS/T2EX) P1.1 2 (ECI) P1.2 3 (CEX0) P1.3 4 (†SS/CEX1) P1.4 5 († ...
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... Pin Description Table 1-1. Atmel AT89LP51RD2/ED2/ID2 Pin Description Pin Number (1) VQFP VQFN PLCC PDIP Symbol RST P4.6 AT89LP51RD2/ED2/ID2 Preliminary 4 Type Description I/O P1 ...
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... Table 1-1. Atmel AT89LP51RD2/ED2/ID2 Pin Description Pin Number (1) VQFP VQFN PLCC PDIP Symbol GND POL P0.3 3714A–MICRO–7/11 ...
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... Atmel's high-density nonvolatile memory technology and are compatible with the industry-standard 80C51 instruction set. The AT89LP51RD2/ED2/ID2 is built around an enhanced CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock ...
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... The TWI and OCD features are not available on the PDIP package. The AT89LP51ID2 is also not available in the PDIP. The features of the AT89LP51RD2/ED2/ID2 make it a powerful choice for applications that need pulse width modulation, high speed I/O, and counting capabilities such as alarms, motor control, corded phones, and smart card readers. 3714A– ...
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... Configurable I/O Port 2 Configurable I/O Port 3 Configurable I/O Port 4 Configurable I/O Dual Analog Comparators Configurable Oscillator A Configurable Oscillator B (AT89LP51ID2) lists the fusible options for the AT89LP51RD2/ED2/ID2. These options maintain their RAM ERAM XRAM 4KB 256 Bytes 2KB Interface UART Watchdog Timer SPI Keyboard Interface Timer 0 ...
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... WS 1-0 XSTK EEE ENBOOT 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary User Configuration Fuses Description Selects between the High Speed Crystal Oscillator, Low Power Crystal Oscillator, External Clock on XTAL1A or Internal RC Oscillator for the source of the system clock when oscillator A is selected. Selects between the 32 kHzCrystal Oscillator, External Clock on XTAL1B or Internal RC Oscillator for the source of the system clock when oscillator B is selected (AT89LP51ID2 Only) ...
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... Reset The RST pin of the AT89LP51RD2/ED2/ID2 has selectable polarity using the POL pin (formerly EA). When POL is high the RST pin is active high with a pull-down resistor and when POL is low the RST pin is active low with a pull-up resistor. For existing AT89C51RD2/ED2/ID2 sockets where EA is tied to VDD, replacing AT89C51RD2/ED2 with AT89LP51RD2/ED2/ID2 will main- tain the active high reset ...
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... I/O Ports The P0, P1, P2 and P3 I/O ports of the AT89LP51RD2/ED2/ID2 may be configured in four differ- ent modes. The default setting depends on the Tristate-Port User Fuse. When the fuse is set all the I/O ports revert to input-only (tristated) mode at power-up or reset. When the fuse is not active, ports P1, P2 and P3 start in quasi-bidirectional mode and P0 starts in open-drain mode ...
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... Security The AT89LP51RD2/ED2/ID2 does not support the external access pin (EA). Therefore it is not possible to execute from external program memory in address range 0000H–1FFFH. When the third Lockbit is enabled (Lock Mode 4) external program execution is disabled for all addresses above 1FFFH. This differs from AT89C51RD2/ED2/ID2 where Lock Mode 4 prevents EA from being sampled low, but may still allow external execution at addresses outside the 8K internal space ...
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... The program memory has a regular linear address space with support for 64K bytes of directly addressable application code. The data memory has 256 bytes of inter- nal RAM and 128 bytes of Special Function Register I/O space. The AT89LP51RD2/ED2/ID2 supports up to 64K bytes of external data memory, with portions of the external data memory space implemented on chip as nonvolatile Flash data memory ...
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... External Program Memory The AT89LP51RD2/ED2/ID2 implements the entire 16-bit program memory space inter- nally. The AT89LP51RD2/ED2/ID2 does not support forcing external execution using the EA pin; however it does include a bank-switching mechanism to allow for external pro- gram memory to be mapped into the upper half of the address space. The FBS bit in the BMSEL ...
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... The setup time from the address to the falling edge of ALE remains the same. However, this behavior can be avoided by setting the DISALE bit prior to any jump above the 8K border. Figure 3-4. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary Executing from External Program Memory AT89LP P1 P0 ...
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... SIG In addition to the 64K code space, the AT89LP51RD2/ED2/ID2 also supports a 512-byte User Signature Array and a 128-byte Atmel Signature Array that are accessible by the CPU. The Atmel Signature Array is initialized with the Device ID in the factory. The User Signature Array is available for user identification codes or constant parameter data. Data stored in the signature array is not secure. Security bits will disable writes to the array ...
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... The external memory space is accessed with the MOVX instructions. Some internal data memory resources are mapped into portions of the external address space as shown in the CPU can access them. The AT89LP51RD2/ED2/ID2 includes 2K bytes of on-chip Extra RAM (EDATA) and 4K bytes of nonvolatile EEPROM data memory (FDATA). 3.3.1 XDATA The external data memory space can accommodate up to 64KB of external memory ...
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... When DISALE = 1 the ALE is weakly pulled high. DISALE must be one in order to use P4 general-purpose I/O. The WS bits in AUXR can extended the RD and WR strobes cycles as shown in Figures 3-13, 3-14 and 3-15 longer AT89LP51RD2/ED2/ID2 Preliminary 18 shows a hardware configuration for accessing up to 64K bytes of external RAM using ...
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... Fast mode. When the ALE is inactive (high) unless an external memory access occurs. AO must be set to use P4 general I/O. Notes: 1. WS1 is only available in Fast mode. WS1 is forced Compatibility mode. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary Section 6.8 on page 49). WS0 XRS2 ...
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... Figure 3-9. CLK ALE Figure 3-10. CLK ALE Figure 3-11. Compatibility Mode External Data Memory Write Cycle (WS0 = 0) AT89LP51RD2/ED2/ID2 Preliminary 20 Fast Mode External Data Memory Write Cycle (WS = 00B SFR DPL or Ri OUT P2 P2 SFR Fast Mode External Data Memory Read Cycle (WS = 00B) ...
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... Figure 3-12. Compatibility Mode External Data Memory Read Cycle (WS0 = 0) Figure 3-13. MOVX with One Wait State (WS = 01B) CLK ALE Figure 3-14. MOVX with Two Wait States (WS = 10B) CLK ALE 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary CLK ALE RD DPL SFR OUT PCH SFR ...
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... EEPROM can be accessed only by 16-bit (MOVX @DPTR) addresses. MOVX @Ri instructions to the EEPROM address range will access data memory in the EDATA or XDATA spaces. Addresses above the EEPROM range are mapped to external data memory (XDATA). This feature is only available on AT89LP51ED2 and AT89LP51ID2. AT89LP51RD2/ED2/ID2 Preliminary ...
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... The EEPROM address space accesses an internal nonvolatile data memory. Writes to EEPROM require a more complex protocol and take several milliseconds to complete. The AT89LP51RD2/ED2/ID2 uses an execute-while-write architecture where the CPU continues to operate while the EEPROM write occurs. The software must poll the state of the EEBUSY flag to determine when the write completes ...
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... Clear bit EEE in EECON register 15. Restore interrupts if disabled in #3 16. The EEBUSY flag is set by hardware to indicate that programming is in progress and that the EEPROM is not available for reading and writing 17. The end of programming is indicated by a hardware clear of EEBUSY AT89LP51RD2/ED2/ID2 Preliminary 24 EEE LDPG EEBUSY ...
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... EEPROM Enable. Set to enable EEPROM and map it into the FDATA space 0000H–0FFFH. Clear to disable EEPROM and access EDATA/XDATA in the 0000H–0FFFH address space. BUSY Busy Flag. Set by hardware when programming is in progress. Cleared by hardware when programming is complete. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary EEE LDPG EEBUSY MOVX ...
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... Extended Stack The AT89LP51RD2/ED2/ID2 provides an extended stack space for applications requiring addi- tional stack memory. By default the stack is located in the 256-byte IDATA space of internal data memory. The IDATA stack is referenced solely by the 8-bit Stack Pointer (SP: 81H). Setting the XSTK bit in AUXR1 (see the EDATA space for up to 2KB of stack memory ...
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... Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write to these unlisted locations, since they may be used in future products to invoke new features. Table 4-1. Atmel AT89LP51RD2/ED2/ID2 SFR Map and Reset Values ...
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... Clock Control Register 0 CKCKON1 AFh Clock Control Register 1 (1) CKSEL 85h Clock Selection Register CLKREG AEh Clock Register (1) OSCCON 85h Oscillator Control Register Note: 1. Present on AT89LP51ID2 Only AT89LP51RD2/ED2/ID2 Preliminary RS1 – – – – – – – ...
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... SBUF 99h Serial Data Buffer SADEN B9h Slave Address Mask SADDR A9h Slave Address BDRCON 9Bh Baud Rate Control BRL 9Ah Baud Rate Reload 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary ET2 ES – – EADC ECMP IP1D PPCH PT2H PHS ...
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... Table 4-10. TWI Controller SFRs Mnemonic Add Name SSCON 93h Synchronous Serial Control SSCS 94h Synchronous Serial Status SSDAT 95h Synchronous Serial Data SSADR 96h Synchronous Serial Address AT89LP51RD2/ED2/ID2 Preliminary TF1 TR1 TF0 TR0 GATE1 C/T1 M11 M01 WDTOVF SWRST WDTEN ...
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... D9h PCA Timer/Counter Mode CL E9h PCA Timer/Counter Low Byte CH F9h PCA Timer/Counter High Byte CCAPM0 DAh PCA Timer/Counter Mode 0 CCAPM1 DBh PCA Timer/Counter Mode 1 CCAPM2 DCh PCA Timer/Counter Mode 2 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary KBLS7 KBLS6 KBLS5 KBLS4 KBE7 KBE6 ...
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... ECh PCA Compare Capture Module 2 L CCAP2L7 CCAP2L6 CCAP2L5 CCAP2L4 CCAP2L3 CCAP2L2 CCAP2L1 CCAP2L0 CCAP3L EDh PCA Compare Capture Module 3 L CCAP3L7 CCAP3L6 CCAP3L5 CCAP3L4 CCAP3L3 CCAP3L2 CCAP3L1 CCAP3L0 CCAP4L EEh PCA Compare Capture Module 4 L CCAP4L7 CCAP4L6 CCAP4L5 CCAP4L4 CCAP4L3 CCAP4L2 CCAP4L1 CCAP4L0 AT89LP51RD2/ED2/ID2 Preliminary – ...
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... Enhanced CPU The AT89LP51RD2/ED2/ID2 uses an enhanced 8051 CPU that runs times the speed of standard 8051 devices ( times the speed of X2 8051 devices). The increase in perfor- mance is due to two factors. First, the CPU fetches one instruction byte from the code memory every clock cycle ...
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... MOVX (1-byte, 2-cycle) 5.3 Multiply–Accumulate Unit (MAC) The AT89LP51RD2/ED2/ID2 includes a multiply and accumulate (MAC) unit that can signifi- cantly speed up many mathematical operations required for digital signal processing. The MAC unit includes a 16-by-16 bit multiplier and a 40-bit adder that can perform integer or fractional multiply-accumulate operations on signed 16-bit input values ...
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... AX (E1H) and BX (F7H) hold the higher order bytes. The 16-by-16 bit multiplication is computed through partial products using the AT89LP51RD2/ED2/ID2’s 8-bit multiplier. The 32-bit signed product is added to the 40-bit M accumulator register. The MAC operation is summarized as follows: All computation is done in signed two’ ...
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... DPTR1 Redirect to B. DPRB selects the source/destination register for MOVC/MOVX instructions that reference DPTR1. DPRB When DPRB = 0, ACC is the source/destination. When DPRB = the source/destination. DPRB does not change the index register for MOVC instructions. AT89LP51RD2/ED2/ID2 Preliminary 36 M Register with Sliding Window Byte 4 ...
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... EX: • In some cases, both data pointers must be used simultaneously. To prevent frequent toggling of DPS, the AT89LP51RD2/ED2/ID2 supports a prefix notation for selecting the opposite data pointer per instruction. All DPTR instructions, with the exception of JMP @A+DPTR, when prefixed with an 0A5H opcode will use the inverse value of DPS (DPS) to select the data pointer ...
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... Data Pointer Update The Dual Data Pointers on the AT89LP51RD2/ED2/ID2 include two features that control how the data pointers are updated. The data pointer decrement bits, DPD1 and DPD0 in AUXR1, configure the INC DPTR instruction to act as DEC DPTR. The resulting operation will depend on DPS as shown in and MOVX ...
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... DPD0 Data Pointer 0 Decrement. When set, INC DPTR instructions targeted to DPTR0 will decrement DPTR0. When cleared, INC DPTR instructions will increment DPTR0. DPD0 also determines the direction of auto-update for DPTR0 when DPU0 = 1. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary DPS = 0 /DPTR DPTR DPTR1++ ...
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... Data Pointer Operating Modes The Dual Data Pointers on the AT89LP51RD2/ED2/ID2 include three additional operating modes that affect data pointer based instructions. These modes are controlled by bits in DSPR. Note that these bits in DSPR should be cleared to zero, disabling these modes, before any calls are made to the Flash API ...
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... Circular Buffers The CBE0 and CBE1 bits in DSPR can configure DPTR0 and DPTR1, respectively, to operate in circular buffer mode. The AT89LP51RD2/ED2/ID2 maps circular buffers into two identically sized regions of EDATA/XDATA. These buffers can speed up convolution computations such as FIR and IAR digital filters. The length of the buffers are set by the value of the FIRD (E3H) regis- ter for up to 256 entries ...
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... AT89LP51RD2/ED2/ID2 Preliminary 42 AT89LP51RD2/ED2/ID2 Extended Instructions Mnemonic Description MAC AB Multiply and accumulate Compare ACC to indirect RAM and CJNE A, @R0, rel jump if not equal Compare ACC to indirect RAM and CJNE A, @R1, rel jump if not equal Move external to ACC ...
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... System Clock The AT89LP51RD2/ED2 has a single system clock that is generated directly from one of three selectable clock sources: on-chip crystal oscillator A in high or low power operation, external clock source on XTAL1A, and the internal 8 MHz RC oscillator. A diagram of the clock subsys- tem is shown in shown in ...
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... An optional 5 MΩ on-chip resistor can be connected between XTAL1A and GND. This resistor can improve the startup characteristics of the oscillator especially at higher frequencies. The resistor can be enabled/disabled with the R1 User Fuse page 190.) Figure 6-3. Note: AT89LP51RD2/ED2/ID2 Preliminary 44 Clock Source A Settings Clock Source A Fuse ...
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... Figure 6-4. 6.3 Internal RC Oscillator The AT89LP51RD2/ED2/ID2 has an Internal RC oscillator tuned to 8.0 MHz ±2.5%. When enabled as clock source A, XTAL1A and XTAL2A may be used as P4.6 and P4.7 respectively. For AT89LP51ID2 the internal oscillator can also be selected for clock source B, freeing up XTAL1B and XTAL2B to act as P1.0 and P4.2 respectively. The frequency of the oscillator may be adjusted within limits by changing the RC Calibration Byte stored at byte 384 of the User Sig- nature Array ...
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... Boot from a fast responding, less accurate oscillator and switch later to a more accurate but slow to stabilize oscillator. Selection of which oscillator drives the system clock is controlled by the CKS bit in CKSEL. In order to switch to a different oscillator, that oscillator must be enabled with the OscAEn or Osc- AT89LP51RD2/ED2/ID2 Preliminary 46 Crystal Oscillator B Connections C1 10– ...
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... OscBEn and CKS) unchanged. Any reset will exit Power- down mode and place these bits in their default states as determined by the user fuse. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary Section 24.2 on page 190). This fuse is also shadowed in the OSC bit of the boot- ...
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... OSCA Enable. Clear to power down the OSCA source. Set to enable the OSCA source. The default state is set by the Oscillator Select user fuse. See 6.7 X1/X2 Feature The AT89LP51RD2/ED2/ID2 includes the X1/X2 feature for compatibility with the existing AT89C51RD2/ED2/ID2. This feature allows a divider-by switched in/out between the oscillator source and the main system clock. This feature is controlled by the X2 bit in CKCON0 (See Table 6-9 on page source, ensuring a 50% duty cycle regardless of the cyclic ratio at the oscillator output ...
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... System Clock Prescaler The AT89LP51RD2/ED2/ID2 includes an 8-bit prescaler that allows the system clock to be divided down from the selected clock source by even numbers in the range 4–1020 in X1 mode and 2–510 in X2 mode. The prescaler can reduce power consumption by decreasing the opera- tional frequency during non-critical periods ...
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... In Compatibility Mode, clear for one system clock period per peripheral clock cycle and set for two clock 1-0 periods per peripheral clock cycle. In Fast Mode, clear for one system clock period and set for TPS+1 clocks per peripheral clock cycle. AT89LP51RD2/ED2/ID2 Preliminary 50 Table 6-8 on page 49). This prescaler is shared among all peripherals and con- ...
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... In Fast Mode, clear for two clock periods per instruction cycle and set for one clock periods per instruction cycle. The default state set by the X2 Fuse. See Figure 6-7. Peripheral Clock Selection Compatibility Mode ÷(TPS+1) SYSTEM CLOCK ÷2 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary Section 24.2 on page ÷2 1 SYSTEM CLOCK Timer Timer 1 ...
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... T2 will toggle at the oscillator frequency. Timer 2 can then use the oscilla- tor as its counter input as well, with no division. For this mode to function correctly, the timer peripheral clock must be running (not in Power-down) and operating at a frequency at least twice as high OSCB as shown in the following equation: AT89LP51RD2/ED2/ID2 Preliminary 52 – – ...
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... AT89LP51RD2/ED2/ID2 has six sources of reset: power-on reset, brown-out reset, external reset, hardware watchdog reset, PCA watchdog reset and software reset. ...
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... Table 7-1. SUT Fuse 1 7.2 Brown-out Reset The AT89LP51RD2/ED2/ID2 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V DD the BOD is nominally 2.0V. The purpose of the BOD is to ensure that if V executing at speed, the system will gracefully enter reset without the possibility of errors induced by incorrect execution ...
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... External Reset The RST pin of the AT89LP51RD2/ED2/ID2 can function as either an active-low reset input active-high reset input. The polarity of the RST pin is selectable using the POL pin (for- merly EA). When POL is high the RST pin is active high with an on-chip pull-down resistor tied to GND ...
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... Reset” on page 107 other than 5AH/A5H or 1EH/E1H to WDTRST will generate an immediate reset and set both WDTOVF and SWRST to flag an error. Software reset will also drive the RST pin active unless DISRTO is set. AT89LP51RD2/ED2/ID2 Preliminary 56 Figure 7-4. In order to properly propagate this pulse to the rest of the ...
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... Idle and Power-down. These modes are accessed through the PCON register. Additional steps may be required to achieve the lowest possible power consumption while using these modes. In addition the AT89LP51RD2/ED2/ID2 has fusible configuration options that can further reduce the active power consumption under certain circumstances. ...
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... The interrupt pin should be held low long enough for the selected clock source to stabilize. After the rising edge on the pin the interrupt service routine will be executed. AT89LP51RD2/ED2/ID2 Preliminary 58 Interrupt Recovery from Power-down (PWDEX = 1) ...
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... For AT89LP51ID2, switch the system clock from a high power oscillator like XTALA to a lower power oscillator like the internal 8 MHz oscillator during periods when frequency accuracy is not as important. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary Interrupt Recovery from Power-down (PWDEX = 0) Figure Table 7-1 on page 54) ...
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... See Table 8-3. Fuse 1 (0EH) 00H (0) FFH (1) — AT89LP51RD2/ED2/ID2 Preliminary 60 User Configuration Fuses Affecting Power Consumption Description The Low Power Crystal Oscillator (setting 2) will use half the power of the High Speed Crystal Oscillator (setting 3) for the same frequency ( ≤ 12 MHz) X2 mode can keep the same CPU speed while cutting the crystal frequency in half ...
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... Interrupts The AT89LP51RD2/ED2/ID2 provides 11 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1 and 2), a serial port interrupt, an SPI interrupt, a key- board interrupt, a PCA interrupt, an analog comparator interrupt and an ADC interrupt. These interrupts and the system reset each have a separate program vector at the start of the program memory space ...
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... Table 9-2. Figure 9-1. INT0 INT1 PCA IT EXF2 KBD IT TWIF SPIF TXE MODF CFA CFB ADIF AT89LP51RD2/ED2/ID2 Preliminary 62 Priority Level Bit Values IPH Interrupt Control Subsystem IEN1, IEN0 IT0 EX0 IE0 ET0 TF0 IT1 EX1 IE1 ET1 TF1 ET2 ...
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... The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective Timers). When a timer interrupt is generated, the on-chip hardware clears the flag that generated it when the service routine is vectored to. All other flags must be cleared by software. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary 9-3. Figure 9-2 63 ...
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... Minimum Interrupt Response Time (Compatibility Mode) 1 Clock Cycles INT0 Ack. IE0 Instruction LCALL Figure 9-5. Maximum Interrupt Response Time (Compatibility Mode) 1 Clock Cycles INT0 IE0 Instruction RETI AT89LP51RD2/ED2/ID2 Preliminary 64 5 LCALL 1st ISR Instr Ack. MOVX @/DPTR, A LCALL 14 ISR 13 Ack. MUL AB 14 1st ISR Instr ...
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... TWI Interrupt Enable ETWI Clear to disable the TWI interrupt. Set to enable the TWI interrupt when Keyboard Interrupt Enable EKBD Clear to disable the Keyboard interrupt. Set to enable the Keyboard interrupt when 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary ET2 ES ET1 EADC ECMP – ...
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... PSPL Low order bit for SPI interrupt priority level. TWI Interrupt Priority Low PTWL Low order bit for TWI interrupt priority level. Keyboard Interrupt Priority Low PKBL Low order bit for Keyboard interrupt priority level. AT89LP51RD2/ED2/ID2 Preliminary 66 PT2L PSL PT1L – ...
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... High order bit for SPI interrupt priority level. TWI Interrupt Priority High PTWH High order bit for TWI interrupt priority level. Keyboard Interrupt Priority High PKBH High order bit for Keyboard interrupt priority level. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary PT2H PSH PT1H – ...
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... External Interrupts The INT0 (P3.2) and INT1 (P3.3) pins of the AT89LP51RD2/ED2/ID2 may be used as external interrupt sources. The external interrupts can be programmed to be level-activated or transition- activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx = 0, external interrupt x is triggered by a detected low at the INTx pin. If ITx = 1, external interrupt x is edge-triggered. In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle, interrupt request flag IEx in TCON is set ...
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... Figure 11-1. Keyboard Block Diagram KBLS 1 (P1.7) GPI7 0 1 (P1.6) GPI6 0 1 (P1.5) GPI5 0 1 (P1.4) GPI4 0 1 (P1.3) GPI3 0 1 (P1.2) GPI2 0 1 (P1.1) GPI1 0 1 (P1.0) GPI0 0 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary KBMOD KBE ...
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... P1.x disabled 1 = interrupt for P1.x enabled . Table 11-4. – Keyboard Interrupt Flag Register KBF KBF = 9EH Not Bit Addressable KBF7 KBF6 Bit 7 6 KBF interrupt on P1.x inactive 1 = interrupt on P1.x active. Must be cleared by software. AT89LP51RD2/ED2/ID2 Preliminary 70 KBMOD5 KBMOD4 KBMOD3 KBLS5 KBLS4 KBLS3 KBE5 KBE4 ...
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... I/O Ports The AT89LP51RD2/ED2/ID2 can be configured for between 36 and 40 I/O pins. The exact num- ber of general I/O pins available depends on the clock and external memory configuration as shown in Table 12-1. Clock Source A External Crystal or Resonator External Clock Internal RC Oscillator Note: 12.1 Port Configuration All port pins on the AT89LP51RD2/ED2/ID2 may be configured in one of four modes: quasi-bidi- rectional (standard 8051 port outputs), push-pull output, open-drain output, or input-only ...
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... When the pin is pulled low externally this pull-up will always source some current. The very weak pull-up is disabled when the port register contains a zero. In addition the very weak pull-ups of all quasi-bidirectional ports can be disabled globally by setting the DPU bit in the AUXR register (See AT89LP51RD2/ED2/ID2 Preliminary 72 Configuration Modes for Port x Pin y PxM1.y ...
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... Figure 12-1. Quasi-bidirectional Output Figure 12-2. Input Only Figure 12-3. Input Circuit for P3.2, P3.3, P4.6 and P4.7 3714A–MICRO–711 AT89LP51RD2/ED2/ID2 Preliminary 1 Clo c k Del Flip-Flop) F rom Register Input ...
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... Port Analog Functions The AT89LP51RD2/ED2/ID2 incorporates two analog comparators and an 8-channel analog-to- digital converter. In order to give the best analog performance and minimize power consump- tion, pins that are being used for analog functions must have both their digital outputs and digital inputs disabled ...
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... SETB PX.Y 12.4 Port Alternate Functions Most general-purpose digital I/O pins of the AT89LP51RD2/ED2/ID2 share functionality with the various I/Os needed for the peripheral units. pins. Alternate functions are connected to the pins in a logic AND fashion. In order to enable the alternate function on a port pin, that pin must have a “1” in its corresponding port register bit, otherwise the input/output will always be “ ...
Page 76
... Table 12-6. PxM0.y Table 12-7. Port Pin P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 AT89LP51RD2/ED2/ID2 Preliminary 76 Pin Function Configurations for Port x Pin y PxM1 Port Pin Alternate Functions Configuration Bits PxM0.y PxM1.y P0M0.0 P0M1.0 P0M0.1 P0M1.1 P0M0.2 P0M1.2 P0M0.3 P0M1.3 P0M0.4 P0M1.4 P0M0.5 P0M1.5 P0M0.6 P0M1.6 P0M0.7 P0M1 ...
Page 77
... Table 12-7. Port Pin P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 3714A–MICRO–711 AT89LP51RD2/ED2/ID2 Preliminary Port Pin Alternate Functions Configuration Bits PxM0.y PxM1.y P1M0.4 P1M1.4 P1M0.5 P1M1.5 P1M0.6 P1M1.6 P1M0.7 P1M1.7 P2M0.0 P2M1.0 P2M0.1 P2M1.1 P2M0.2 P2M1.2 P2M0.3 P2M1.3 P2M0.4 P2M1.4 P2M0.5 P2M1.5 P2M0.6 P2M1.6 P2M0.7 P2M1.7 P3M0.0 P3M1 ...
Page 78
... Table 12-7. Port Pin P3.7 P4.0 P4.1 P4.2 P4.4 P4.5 P4.6 P4.7 AT89LP51RD2/ED2/ID2 Preliminary 78 Port Pin Alternate Functions Configuration Bits PxM0.y PxM1.y P3M0.7 P3M1.7 P4M0.0 P4M1.0 P4M0.1 P4M1.1 P4M0.2 P4M1.2 P4M0.4 P4M1.4 P4M0.5 P4M1.5 P4M0.6 P4M1.6 P4M0.7 P4M1.7 Alternate Function Notes RD SCL open-drain SDA open-drain OSCB must be disabled or in XTAL2B internal oscillator or external clock modes to use P4 ...
Page 79
... Enhanced Timer 0 and Timer 1 with PWM The AT89LP51RD2/ED2/ID2 has two 16-bit Timer/Counters, Timer 0 and Timer 1, with the fol- lowing features: • Two 16-bit timer/counters with 16-bit reload registers • Two independent 8-bit precision PWM outputs with 8-bit prescalers • UART or SPI baud rate generation using Timer 1 • ...
Page 80
... Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 0 Type IT0 Set/cleared by software to specify falling edge/low level triggered external interrupts. AT89LP51RD2/ED2/ID2 Preliminary 80 lists the registers used by Timer 0/1. TCON, TCONB and TMOD are detailed below. Timer 0/1 Register Summary Address ...
Page 81
... T0M0 Mode T0M1 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary T1M1 T1M0 GATE0 T1M0 Operation Variable Timer Mode. 8-bit Timer/Counter TH1 with TL1 as 1–8 bit prescaler. Default bits for a 13-bit timer/counter compatible with AT89C51RD2/ED2/ID2. 16-bit Auto-Reload Mode. TH1 and TL1 are cascaded to form a 16-bit Timer/Counter 1 which is reloaded from RH1 and RL1 when it overflows ...
Page 82
... TnX2 in Compatibility Mode will double the timeout period. Mode 0 operation is the same for Timer 0 as for Timer 1, except that TR0, TF0, GATE0 and INT0 replace the corresponding Timer 1 signals in one for Timer 1 (TMOD.6) and one for Timer 0 (TMOD.2). AT89LP51RD2/ED2/ID2 Preliminary 82 PSC12 PSC11 ...
Page 83
... The following equation gives the timeout period for Mode 1. In Fast Mode, TPS applies only when the TnX2 bits in CKCON0 are set. TPS always applies in Compatibility Mode, therefore setting TnX2 in Compatibility Mode will double the timeout period. Figure 13-2. Timer/Counter 1 Mode 1: 16-bit Auto-Reload INT1 Pin 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary CLK ÷TPS SYS C C ...
Page 84
... TMOD but cannot generate an interrupt. Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the AT89LP51RD2/ED2/ID2 can appear to have four Timer/Counters. When Timer Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt ...
Page 85
... Figure 13-4. Timer/Counter 0 Mode 3: Two 8-bit Counters 13.6 Pulse Width Modulation On the AT89LP51RD2/ED2/ID2, Timer 0 and Timer 1 may be independently configured as 8-bit asymmetrical (edge-aligned) pulse width modulators (PWM) by setting the PWM0EN or PWM1EN bits in TCONB, respectively. In PWM Mode the generated waveform is output on the timer's input pin T1. Therefore, C/Tx must be set to “0” when in PWM mode and the T0 (P3 ...
Page 86
... When the count in THn matches OCRn, the output pin is cleared low. The following formu- las give the output frequency and duty cycle for Timer n in PWM Mode 1. Timer 1 in PWM Mode 1 is identical to Timer 0. Note: AT89LP51RD2/ED2/ID2 Preliminary 86 f out Mode 0: Duty Cycle % In Fast Mode, TPS applies only when the TnX2 bits in CKCON0 are set ...
Page 87
... Figure 13-9 on page used to output a square wave of varying frequency. THn acts as an 8-bit counter. The following formula gives the output frequency for Timer n in PWM Mode 2. Note: Figure 13-8. Timer/Counter 1 PWM Mode 2 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary ÷TPS CLK SYS Control TR1 88). Timer 1 in PWM Mode 2 is identical to Timer 0. PWM Mode 2 can be ...
Page 88
... AT89LP51RD2/ED2/ID2 can appear to have four Timer/Counters. When Timer PWM Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt ...
Page 89
... Figure 13-10. Timer/Counter 0 PWM Mode 3 14. Timer 2 The AT89LP51RD2/ED2/ID2 includes a 16-bit Timer/Counter 2 with the following features: • 16-bit timer/counter with one 16-bit reload/capture register • One external reload/capture input • Up/Down counting mode with external direction control • UART baud rate generation • ...
Page 90
... Table 14-1. RCLK + TCLK The following definitions for Timer 2 are used in the subsequent paragraphs: Table 14-2. Symbol MIN MAX BOTTOM AT89LP51RD2/ED2/ID2 Preliminary 90 f SYS f = ----------------------------------------------- - TIMER T2X2 × TPS f SYS = ...
Page 91
... TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. Note: The Timer 2 operating mode depends on bits in both T2CON and T2MOD as shown in bits have priority over CP/RL2. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary Table 14-4). The register pair {TH2, TL2} at addresses 0CDH and 0CCH are the RCLK TCLK ...
Page 92
... RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 and TF2 bits can generate an interrupt. Capture mode is illustrated in The Timer 2 overflow rate in Capture mode is given by the following equation: Note: Figure 14-1. Timer 2 Diagram: Capture Mode T2EX PI N AT89LP51RD2/ED2/ID2 Preliminary 92 – – – 5 ...
Page 93
... The Timer 2 overflow rate for this mode is given in the following equation: Auto-Reload Mode: Note: Figure 14-2. Timer 2 Diagram: Auto-Reload Mode (DCEN = 0) 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary Table 14-4). Upon reset, the DCEN bit is set that timer 2 will default to Summary of Auto-Reload Modes T2EX ...
Page 94
... Changes to the count direction may result in longer or shorter periods between time-outs. Figure 14-4. Timer 2 Waveform: Auto-Reload Mode (DCEN = 1) AT89LP51RD2/ED2/ID2 Preliminary 94 MAX BOTTOM MIN = 00B, the timer will overflow at MAX and set the TF2 bit ...
Page 95
... RCAP2L) to (TH2, TL2). Thus when Timer use as a baud rate gen- erator, T2EX can be used as an extra external interrupt. Also note that the Baud Rate and Frequency Generator modes may be used simultaneously. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary ÷TPS Modes 1 and 3 Baud Rates Modes 1, 3 ...
Page 96
... Timer 2 is used as a baud-rate generator possible to use Timer baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L. Figure 14-7. Timer 2 in Clock-out Mode AT89LP51RD2/ED2/ID2 Preliminary 96 CLK SYS C/ ...
Page 97
... The PCA timer is a common time base for all five modules (see source is determined from the CPS1 and CPS0 bits in the CMOD register be programmed to run at: • 1/6 the • 1/2 the • The Timer 0 overflow • The input on the ECI pin (P1.2) 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary ÷ ) (TPS+1) PERIPH ÷ ...
Page 98
... The CCON register contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module (Refer to • Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit. AT89LP51RD2/ED2/ID2 Preliminary 98 Section 15.7) 0 ÷ ...
Page 99
... CH – PCA Counter Register High CH Address = 0F9H Not Bit Addressable C15 C14 Bit 7 6 Symbol Function Module n Compare/Capture Register High C 15-8 Holds the higher order bits of the 16-bit PCA Timer/Counter. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary – CCF4 CCF3 C13 C12 C11 Figure 15-2. ...
Page 100
... The ECCF bit (CCAPMn.0 where depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. • PWM (CCAPMn.1) enables the pulse width modulation mode. AT89LP51RD2/ED2/ID2 Preliminary 100 C5 C4 ...
Page 101
... Set to configure Module n in PWM mode and use CEXn as a PWM output. Clear to disable PWM mode for Module n. Enable CCFn Interrupt ECCFn Clear to disable the CCFn bit in CCON as an interrupt source. Set to enable the CCFn bit in CCON to generate interrupts. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary shows the CCAPMn settings for the various PCA functions. CAPPn CAPNn MATn ...
Page 102
... CCAP3L Address = 0EDH CCAP4L Address = 0EEH Not Bit Addressable CCAPn.7 CCAPn.6 Bit 7 6 Symbol Function Module n Compare/Capture Register Low CCAPn 7-0 Holds the lower order bits of the 16-bit Compare/Capture value for Module n. AT89LP51RD2/ED2/ID2 Preliminary 102 TOGn PWMn ECCFn ...
Page 103
... CCAPnL will clear ECOM so that an unwanted match doesn’t occur while modify- ing the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary CL CAPPn CCAPnL CCAPnH CCAPMn.5 CAPNn CCAPMn ...
Page 104
... ECOM bit can still be controlled by accessing to CCAPMn register. An example of a High Speed Output waveform is shown in output can be controlled by reloading the PCA Timer in software and/or changing the compare values multiple times per timeout period. Figure 15-6. High Speed Output Waveform {CH,CL} = FFFFH {CCAPnH,CCAPnL} {CH,CL} = 0000H AT89LP51RD2/ED2/ID2 Preliminary 104 Figure 15-5 Write to Write to ...
Page 105
... The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. The following equations show the resulting frequency and duty cycles of the generated output: Figure 15-7. PCA PWM Mode An example PCA PWM waveform is shown in Figure 15-8. PCA PWM Waveform 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary CPS 00B: = Duty Cycle % = CL ...
Page 106
... Between the two write instructions, SFR reads are allowed, but writes are not allowed. The instructions should move 1EH to the WDTRST register and then 1EH to the WDTRST register. An incorrect feed or enable sequence will cause an immediate watchdog reset. AT89LP51RD2/ED2/ID2 Preliminary 106 Figure 15-4 shows a diagram of how the watchdog works ...
Page 107
... The WDT time-out period is dependent on the system clock frequency. 16.1 Software Reset A Software Reset of the AT89LP51RD2/ED2/ID2 is accomplished by writing the software reset sequence 5AH/A5H to the WDTRST SFR. The WDT does not need to be enabled to generate the software reset. A normal software reset will set the SWRST flag in WDTCON. However any time an incorrect sequence is written to WDTRST (i ...
Page 108
... The WDT is enabled by writing the sequence 1EH/E1H to the WDTRST SFR. The current status may be checked by reading the WDTEN bit in WDTCON. To prevent the WDT from resetting the device, the same sequence 1EH/E1H must be written to WDTRST before the time-out interval expires. A software reset is generated by writing the sequence 5AH/A5H to WDTRST. AT89LP51RD2/ED2/ID2 Preliminary 108 WDTEN ...
Page 109
... Serial Interface (UART) The serial interface on the AT89LP51RD2/ED2/ID2 implements a Universal Asynchronous Receiver/Transmitter (UART). The UART has the following features: • Full-duplex Operation • Data Bits • Framing Error Detection • Multiprocessor Communication Mode with Automatic Address Recognition • Baud Rate Generator Using Timer 1, Timer 2 or dedicated Internal Baud Rate Generator • ...
Page 110
... Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. Notes: 1. SMOD0 is located at PCON. system frequency. The baud rate depends on SMOD1 (PCON.7). SYS AT89LP51RD2/ED2/ID2 Preliminary 110 SM2 REN TB8 5 4 ...
Page 111
... If SMOD1 = 1, the baud rate is 1/16 of the system fre- quency, as shown in the following equation: The baud rate in Modes 1 and 3 is generated from one of Timer 1, Timer 2 or the Internal Baud Rate Generator as detailed in 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary See “Automatic Address Recognition” on page 116. SMOD1 Mode 0 Baud Rate 2 × ...
Page 112
... In the most typical applica- tions configured for timer operation in auto-reload mode (high nibble of TMOD = 0010B). In this case, the baud rate is given by the following formula: Table 17-3 AT89LP51RD2/ED2/ID2 Preliminary 112 UART Baud Rate Selection Table for Modes 1 and 3 RCLK TBCK (T2CON ...
Page 113
... RCAP2H and RCAP2L, which are preset by software. In this case, the baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the following equation: Table 17-4 that TPS and T2X2 do not apply to Timer 2 in baud rate mode. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary X2 SMOD1 C ...
Page 114
... Internal Baud Rate Generator (BRG) The AT89LP51RD2/ED2/ID2 includes an Internal Baud Rate Generator (BRG) for UART modes 1 and 3 that can free up Timer 1 or Timer 2 for other uses. The BRG is an 8-bit counter with reload as shown in is controlled by the BDRCON register (See SPD bit determines the clock source: either the system clock divided-by-6 or the system clock with no division. The BRG is not affected by the Timer Prescaler ...
Page 115
... Symbol Function Baud Rate Reload Value BRL Holds the 8-bit reload value of the Internal Baud Rate Generator. This value is loaded into the BRG when the BRG 7-0 overflows from FFH to 00H. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary ÷6 CLK 0 SYS 1 SPD BRR (BDRCON.1) (BDRCON ...
Page 116
... Using the Automatic Address Recognition feature allows a master to selectively com- municate with one or more slaves by invoking the given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Automatic Address Recognition is not available during Mode 0. AT89LP51RD2/ED2/ID2 Preliminary 116 – BRR ...
Page 117
... Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51- type UART drivers which do not make use of this feature. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00X0 ...
Page 118
... SMOD1 has an effect on the relationship between the clock and data as described below. The baud rate can also be generated by Timer 1 by setting TB8 in SCON or the Internal Baud Rate Generator by setting SRC in BDRCON. Table 17-10. Mode 0 Baud Rates SRC AT89LP51RD2/ED2/ID2 Preliminary 118 Table 17-10 TB8 SMOD1 ...
Page 119
... Mode 0 transfers data LSB first whereas SPI or TWI are generally MSB first. Emulation of these interfaces may require bit reversal of the transferred data bytes. The following code example reverses the bits in the accumulator: EX: REVRS: RLC 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary Table 17-11 and shown in SMOD1 Clock Idle 0 ...
Page 120
... SMOD1 = 1 TXD SM2 = 0 RXD (TX) RXD (RX) SMOD1 = 0 TXD SM2 = 1 RXD (TX) RXD (RX) SMOD1 = 1 TXD SM2 = 1 RXD (TX) RXD (RX) Figure 17-3. UART Mode 0 TWI Emulation (SMOD1 = 1) (SCL) TXD 0 (SDA) RXD SM2 P3.0 Write to SBUF TI AT89LP51RD2/ED2/ID2 Preliminary 120 ...
Page 121
... SMOD1 WRITE SEND SHIFT RXD ( OUT ) TXD (SHIFT CLOCK) TI WRITE T O SCON (CLEAR RECEIVE SHIFT RXD ( TXD (SHIFT CLOCK) 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary INTERNAL “1“ INTERNAL SM2 121 ...
Page 122
... On receive, the stop bit goes into RB8 in SCON. In the AT89LP51RD2/ED2/ID2, the baud rate is determined either by the Timer 1 overflow rate, the TImer 2 overflow rate, or both. In this case one timer is for transmit and the other is for receive. ...
Page 123
... WRITE TO SBUF SEND DATA SHIFT D0 TXD START BIT TI ÷16 RESET RX CLOCK RXD START BIT BIT DETECTOR SAMPLE TIMES SHIFT RI 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary INTERNAL BUS “1” SBUF CL ZERO DETECTOR SHIFT DATA START TX CONTROL ÷16 RX CLOCK SEND TI TI SERIAL PORT ÷ ...
Page 124
... SBUF. One bit time later, whether the above conditions were met or not, the unit continues look- ing for a 1-to-0 transition at the RXD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8, or RI. AT89LP51RD2/ED2/ID2 Preliminary 124 show a functional diagram of the serial port in Modes 2 and 3. The ...
Page 125
... Figure 17-6. Serial Port Mode 2 CPU CLOCK SMOD1 1 SMOD1 0 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary INTERNAL BUS INTERNAL BUS 125 ...
Page 126
... WRITE TO SBUF SEND DATA SHIFT D0 D1 TXD START BIT TI STOP BIT GEN ÷16 RESET RX CLOCK RXD START BIT BIT DETECTOR SAMPLE TIMES SHIFT RI AT89LP51RD2/ED2/ID2 Preliminary 126 INTERNAL BUS TB8 SBUF CL ZERO DETECTOR STOP BIT SHIFT DATA START TX CONTROL ÷16 RX CLOCK SEND ...
Page 127
... Enhanced Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed, full-duplex synchronous data transfer between the AT89LP51RD2/ED2/ID2 and peripheral devices or between multiple microcon- troller devices, including multiple masters and slaves on a single bus. The SPI includes the following features: • Full-duplex, 3-wire or 4-wire Synchronous Data Transfer • ...
Page 128
... In master mode, the baud rate of SCK is determined by the SPR bits in SPCON. The SPR bits select a value from a 7-bit prescaler on the system clock or the Timer 1 overflow. In slave mode the clock rate is set by the master device; the slave need not AT89LP51RD2/ED2/ID2 Preliminary 128 Master ...
Page 129
... Clearing SSDIS control bit does not clear MODF. 2. Special care should be taken when setting SSDIS control bit when CPHA = ’0’ because in this mode the SS is used to start the transmission on some devices. This requirement does not apply to the AT89LP51RD2/ED2/ID2 itself. (2) . This kind of ...
Page 130
... For more details on port configuration, refer to . Table 18-2. Pin SCK MOSI MISO Notes: AT89LP51RD2/ED2/ID2 Preliminary 130 “Port Configuration” on page SPI Pin Configuration and Behavior when SPE = 1 Mode Master (MSTR = 1) Quasi-bidirectional Output Push-Pull Output ...
Page 131
... Master Operation An SPI master device initiates all data transfers on the SPI bus. The AT89LP51RD2/ED2/ID2 is configured for master operation by setting MSTR = 1 in SPCON. Writing to the SPI data register (SPDAT) while in master mode loads the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer is moved to the shift register ...
Page 132
... Slave devise has not cleared the SPIF bit issuing from the previous data Byte transmitted. In this case, the receiver buffer contains the Byte sent after the SPIF bit was last cleared. A read of the SPDAT returns this Byte. All others Bytes are lost. This condition is not detected by the SPI peripheral. AT89LP51RD2/ED2/ID2 Preliminary 132 3714A–MICRO–7/11 ...
Page 133
... SCK CYCLE # (FOR REFERENCE) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (FROM MASTER) MISO (FROM SLAVE) SS (TO SLAVE) Note: *Not defined but normally LSB of previously transmitted character. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary Figures 18-3 and 18-4. To prevent glitches on SCK from disrupting the MSB ...
Page 134
... Set up the clock mode before enabling the SPI: set all bits needed in SPCON except the SPEN bit, then set SPEN. 2. Enable the master SPI prior to the slave device. 3. Slave echoes master on the next Tx if not loaded with new data. AT89LP51RD2/ED2/ID2 Preliminary 134 SSDIS ...
Page 135
... When cleared the SPI pins are in the default locations on Port 1 that are compatible with AT89C51RD2/ED2/ID2. When set the pins are shuffled on Port 1 to match the AT89S8253 or AT89LP6440 devices. See TX Buffer Interrupt Enable TBIE When TBIE = 1, TXE will generate an SPI interrupt if ESP = 1. When TBIE = 0, TXE does not generate an interrupt. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary SPD5 SPD4 SPD3 5 4 ...
Page 136
... AT89LP51RD2/ED2/ID2 Preliminary 136 Figure 19-1 The TWI is available on both the AT89LP51RD2 and AT89LP51ED2 where as it was not available on the AT89C51RD2 and AT89C51ED2. The TWI is not available in the PDIP package. Device 1 Device 3 Device 2 ...
Page 137
... When a slave recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL (ACK) cycle. If the addressed Slave is busy, or for some other reason can not service the Mas- 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary SDA SCL Data Stable ...
Page 138
... Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first. Figure 19-5. Data Packet Format Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master AT89LP51RD2/ED2/ID2 Preliminary 138 Addr MSB 1 2 START Data MSB 1 2 SLA+R/W Addr LSB ...
Page 139
... Note that all masters listen to the SCL line, effectively starting to count their SCL high and low Time-out periods when the combined SCL line goes high or low, respectively. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary shows a typical data transmission. Note that several data bytes can be transmitted Addr LSB R/W ...
Page 140
... M SDA Line Synchronized SCL Line Note that arbitration is not allowed between: • A REPEATED START condition and a data bit. • A STOP condition and a data bit. • A REPEATED START and a STOP condition. AT89LP51RD2/ED2/ID2 Preliminary 140 TA low Line TB low Masters Start Counting Low Period ...
Page 141
... CPU clock frequency in the slave must be at least 16 times higher than the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period. The SCL frequency is generated according to 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary SCL SDA Slew-rate ...
Page 142
... As long as the SI flag is set, the SCL line is held low. This allows the application software to complete its tasks before allowing the TWI transmission to continue. The SI flag is set in the following situations: AT89LP51RD2/ED2/ID2 Preliminary 142 TWI Bit Rate Configuration F ...
Page 143
... Bit Control Rate 1 CR1 Sets the bit rate for TWI master mode along with C0 and CR2. See Bit Control Rate 02 CR0 Sets the bit rate for TWI master mode along with C1 and CR2. See 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary STA STO ...
Page 144
... TWI byte transfer. Note that the TWI Interrupt Enable (ETWI) bit in IE2 together with the Global Interrupt Enable bit in EA allow the application to decide whether or not assertion of the SI flag should generate an AT89LP51RD2/ED2/ID2 Preliminary 144 SC5 ...
Page 145
... The TWI will not start any operation as long as the SI bit in SSCON is set. Immediately after the application has cleared SI, the TWI will initiate transmission of the address packet. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary is a simple example of how the application can interface to the TWI hardware Check SSCS to see if SLA+W was sent and ACK received. ...
Page 146
... It is the application software that decides which modes are legal. The following sections describe each of these modes. Possible status codes are described along with figures detailing data transmission in each of the modes. These figures contain the following abbreviations: AT89LP51RD2/ED2/ID2 Preliminary 146 3714A–MICRO–7/11 ...
Page 147
... SI bit should be cleared to continue the transfer. This scheme is repeated until the last byte has been sent and the transfer is ended by generating a STOP condition or a repeated START con- dition. A STOP condition is generated by writing the following value to SSCON: 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary to Figure 19-14, circles are used to indicate that the SI flag is set. The numbers ...
Page 148
... SLA+W has been 18h transmitted; ACK has been received SLA+W has been 20h transmitted; NOT ACK has been received Data byte has been 28h transmitted; ACK has been received AT89LP51RD2/ED2/ID2 Preliminary 148 CR2 SSIE STA STO bit rate 1 0 CR2 SSIE STA ...
Page 149
... This scheme is repeated until the last byte has been received. After the last byte has been received, the MR should inform the ST by sending a NACK after the last received data byte. The transfer is ended by generating a STOP condition or a repeated START condition. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary Load data byte ...
Page 150
... Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost in slave address or data byte Arbitration lost and addressed as slave From master to slave From slave to master AT89LP51RD2/ED2/ID2 Preliminary 150 DATA 18h A P 20h Other master ...
Page 151
... NOT ACK has been received Data byte has been 50h received; ACK has been returned Data byte has been 58h received; NOT ACK has been returned 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary Application Software Response To SSCON To/from SSDAT STA STO SI Load SLA ...
Page 152
... The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address (00h), otherwise it will ignore the general call address.: SSCON Value AT89LP51RD2/ED2/ID2 Preliminary 152 ...
Page 153
... General call 78h address has been received; ACK has been returned Previously addressed with own SLA+W; data has been 80h received; ACK has been returned 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary Application Software Response To SSCON To/from SSDAT STA STO SI No action X 0 ...
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... Previously addressed with general call; data has been 98h received; NOT ACK has been returned A STOP condition or repeated START condition A0h has been received while still addressed as slave AT89LP51RD2/ED2/ID2 Preliminary 154 Read data byte Read data byte Read data byte ...
Page 155
... Reception of the general call address and one or more data bytes Last data byte received is not acknowledged Arbitration lost as master and addressed as slave by general call From master to slave From slave to master 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary SLA W A DATA 60h A 68h General Call A ...
Page 156
... S slave address and one or more data bytes Arbitration lost as master and addressed as slave Last data byte transmitted. Switched to not addressed slave (TWEA = '0') From master to slave From slave to master AT89LP51RD2/ED2/ID2 Preliminary 156 SLA R A DATA A8h A B0h Any number of data bytes DATA ...
Page 157
... TWI is not involved in a serial transfer. Status 00h indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus error occurs when a START or STOP condition occurs at an illegal position in the format frame. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary Application Software Response To SSCON To/from SSDAT ...
Page 158
... REPEATED START between the transmission of the address byte and reception of the data. After a REPEATED START, the Master keeps ownership of the bus. The following figure shows the flow in this transfer. Figure 19-15. Combining Several TWI Modes to Access a Serial EEPROM START AT89LP51RD2/ED2/ID2 Preliminary 158 Application Software Response To SSCON To/from SSDAT STA ...
Page 159
... Dual Analog Comparators The AT89LP51RD2/ED2/ID2 provides two analog comparators. The analog comparators have the following features: • Internal 3-level Voltage Reference (1.125V, 1.25V, 1.375V) • Four Shared Analog Input Channels – Configure as Multiple Input Window Comparator • Selectable Interrupt Conditions – High- or Low-level – ...
Page 160
... When the channel is selected, the source must drive the input capacitance of the comparator through the series resistance (com- bined resistance in the input path). Figure 20-2. Equivalent Analog Input Model AT89LP51RD2/ED2/ID2 Preliminary 160 bits in ACSRx (See 2-0 The flags may be polled by software or may be used to generate an inter- 2-0 ...
Page 161
... Timer 1 overflows after this event. When Timer 1 is selected for the sampling clock, this means the interrupt will occur on the second overflow after the overflow that sampled desired event. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary or RFA bits in AREF. The internal reference voltage, V 1-0 1-0 ...
Page 162
... AIN0 + AIN1 - V AREF CSA = 00/01 RFA = 10 e. 2-channel comparator with external reference & comparator with internal reference AIN0 + AIN2 - AIN1 CSA = 00/10 RFA = 00 AT89LP51RD2/ED2/ID2 Preliminary 162 + AIN3 B CMPA - AIN2 CSB = 11 RFB = CMPA - + A CMPA - ...
Page 163
... Notes: 1. CONA must be cleared to 0 before changing CSA 2. Debouncing modes require the use of Timer 1 to generate the sampling delay. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary CONA CFA 5 4 (1) A+ Channel AIN0 (P2.4) AIN1 (P2.5) AIN2 (P2.6) AIN3 (P2.7) CMA0 Interrupt Mode 0 ...
Page 164
... Notes: 1. CONB must be cleared to 0 before changing CSB 2. Debouncing modes require the use of Timer 1 to generate the sampling delay. AT89LP51RD2/ED2/ID2 Preliminary 164 CONB CFB CENB 5 4 (1) CMB0 Interrupt Mode 0 Negative (Low) level 1 Positive edge (2) 0 Toggle with debouncing ...
Page 165
... RFA1 RFA0 Notes: 1. CONB (ACSRB.5) must be cleared to 0 before changing RFB[1-0]. 2. CONA (ACSRA.5) must be cleared to 0 before changing RFA[1-0]. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary RFB1 RFB0 5 4 (1) B- Channel AIN2 (P2.6) Internal V (~1.125V) AREF-Δ Internal V (~1.25V) AREF Internal V (~1 ...
Page 166
... Digital-to-Analog/Analog-to-Digital Converter The AT89LP51RD2/ED2/ID2 includes a 10-bit Data Converter (DADC) with the following features: • Digital-to-Analog (DAC) or Analog-to-Digital (ADC) Mode • 10-bit Resolution • 6.5 µs Conversion Time • 7 Multiplexed Single-ended Channels or 3 Differential Channels • Internal Temperature Sensor or Supply Voltage Channels • ...
Page 167
... R VDD GND INTERNAL 1.0V REFERENCE P0.6 TEMP VDD/8 P0.5 P0.4 INPUT P0.3 P0.2 P0.1 P0.0 INPUT VDD/2 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary Timer Overflows ADC INPUT SELECT REGISTER (DADI) CHANNEL SELECTION TRIGGER SELECT DA+ SAMPLE & HOLD POS. + MUX - DA- NEG. MUX INTERRUPT FLAG 15 ADC CTRL & STATUS ADC DATA REGISTER ...
Page 168
... ACON must be set back to one after ACS is updated. ACON and ACS should not be changed while a conversion is in progress. ADC input channels must have their port pins configured for input-only mode. The AT89LP51RD2/ED2/ID2 also includes an on-chip temperature sensor and voltage supply channel. These features are available when ACS = 6 ...
Page 169
... V The DAC is enabled by setting the ADCE and DAC bits in DADC. Some settling time is required for the reference circuits to stabilize after the DAC is enabled. The DAC does not have multiple 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary One Conversion ...
Page 170
... Conversely, the DADC clock can be generated directly from the system oscillator using a 7-bit prescaler. The prescaler output is controlled by the ACK bits in DADC as shown in Figure 21-6. The prescaler is independent of any X2 or CKRL division used for the CPU clock. AT89LP51RD2/ED2/ID2 Preliminary 170 Figure One Conversion ...
Page 171
... Place the CPU in Idle during a conversion. For best results, use a Timer to start the conversion while CPU is already in Idle Mode. • If any Port 0 pins are used as digital outputs essential that these do not switch while a conversion is in progress. 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary 7-BIT ADC PRESCALER OSC INTERNAL ÷ 4 ...
Page 172
... X1/X2 and CKRL dividers. OSC Table 21-3. – DADC Input Control Register DADI DADI = A5H Not Bit Addressable ACON IREF Bit 7 6 AT89LP51RD2/ED2/ID2 Preliminary 172 DAC ADCE LADJ (1) Clock Source Internal RC Oscillator/4 (2MHz) f ...
Page 173
... IREF = 1. Otherwise V TEMP Table 21-4. – DADC Data Low Register DADL DADL = ACH Not Bit Addressable ADC.7 ADC.6 Bit 7 6 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary Trigger Software (GO bit) Timer 0 Overflow Timer 1 Overflow Timer 2 Overflow ACS1 ACS0 P0.0 ...
Page 174
... ADC.14 Bit 7 6 Note: When LADJ = 0, bits 9–8 of the ADC result are found in bits 1–0 of DADH. Bits 7–2 are signed extended copies of bit 1. When LADJ = 1, bits 9–2 of the ADC result are found in bits 7–0 of DADH. AT89LP51RD2/ED2/ID2 Preliminary 174 ADC.13 ADC.12 ADC. ...
Page 175
... Instruction Set Summary The AT89LP51RD2/ED2/ID2 is fully binary compatible with the 8051 instruction set. In Compati- bility mode the AT89LP51RD2/ED2/ID2 has identical execution time with AT89C51RD2/ED2 and other standard 8051s. The difference between the AT89LP51RD2/ED2/ID2 in Fast mode and the standard 8051 is the number of cycles required to execute an instruction. Fast mode instructions may take clock cycles to complete ...
Page 176
... ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data RL A RLC RRC A AT89LP51RD2/ED2/ID2 Preliminary 176 Instruction Execution Times and Exceptions ( (2) 2 ...
Page 177
... MOVX A, @/DPTR MOVX @Ri, A MOVX @DPTR, A MOVX @/DPTR, A PUSH direct POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri Bit Operations CLR C CLR bit 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary Instruction Execution Times and Exceptions 1 Bytes ...
Page 178
... LJMP addr16 JMP @A+DPTR JMP @A+PC CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel CJNE @Ri, #data, rel CJNE A, @R0, rel CJNE A, @R1, rel DJNZ Rn, rel DJNZ direct, rel NOP Notes: AT89LP51RD2/ED2/ID2 Preliminary 178 Instruction Execution Times and Exceptions ...
Page 179
... A5 Operation: BREAK (PC) ← (PC 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary defaults the clock cycle is twice the oscillator period, or conversely the clock count is half the number of oscillator periods. 2. This escaped instruction is an extension to the instruction set. 3. This is the minimum time for MOVX with no wait states. In Compatibility mode an additional 24 clocks are added for the wait state. In Fast mode, 1 clock is added for each wait state (0– ...
Page 180
... Function: Clear MAC Accumulator Description: CLR M clears the 40-bit M register. No flags are affected. Example: The M registercontains 123456789AH. The following instruction, CLR M leaves the M register set to 0000000000H. Bytes: 2 Cycles: 2 Encoding: A5 Operation: JMP (M) ← 0 AT89LP51RD2/ED2/ID2 Preliminary 180 ...... ...... ; ACC = @R0. ...... ...... ;ACC > @R0 ...
Page 181
... AJMP LABEL3 If the Accumulator equals 04H when starting this sequence, execution jumps to label LABEL2. Because AJMP is a 2-byte instruction, the jump instructions start at every other address. Bytes: 2 Cycles: 3 Encoding: A5 Operation: JMP (PC) ← (A) + (PC 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary ...
Page 182
... DB 77H DB 88H DB 99H If the subroutine is called with the Accumulator equal to 01H, it returns with 77H in the Accumulator. Bytes: 2 Cycles: 4 Encoding: A5 Operation: MOVC IF (DPS THEN (A) ← ( (A) + (DPTR1) ) ELSE (A) ← ( (A) + (DPTR0) ) AT89LP51RD2/ED2/ID2 Preliminary 182 3714A–MICRO–7/11 ...
Page 183
... Data Pointer: DPH1 hold 56H and DPL1 holds 78H. Bytes: 2 Cycles: 3 Encoding: A5 Operation: MOV IF (DPS THEN (DP1H) ← #data (DP1L) ← #data ELSE (DP0H) ← #data (DP0L) ← #data 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary immed. data 15-8 15-8 7-0 15-8 7 immed ...
Page 184
... Example: DPS = 0, DPTR0 contains 0123H and DPTR1 contains 4567H. The following instruction sequence, MOVX A, @DPTR MOVX @/DPTR, A copies the data from address 0123H to 4567H. Bytes: 2 Cycles: 3 (EDATA) 5 (FDATA or XDATA) Encoding: A5 Operation: MOVX IF (DPS THEN ((DPTR1)) ← (A) ELSE ((DPTR0)) ← (A) AT89LP51RD2/ED2/ID2 Preliminary 184 3714A– ...
Page 185
... On-Chip Debug System The AT89LP51RD2/ED2/ID2 On-Chip Debug (OCD) System uses a two-wire serial interface to control program flow; read, modify, and write the system state; and program the nonvolatile memory. The OCD System has the following features: • Complete program flow control • Read-Modify-Write access to all internal SFRs and data memories • ...
Page 186
... NOP when OCD is disabled. 23.3 Limitations of On-Chip Debug The AT89LP51RD2/ED2/ID2 is a fully-featured microcontroller that multiplexes several functions on its limited I/O pins. Some device functionality must be sacrificed to provide resources for On- Chip Debugging. The On-Chip Debug System has the following limitations: • The Debug Clock pin (DCL) is physically located on the same pin as the External Reset (RST) ...
Page 187
... Flash Memory Programming The Atmel AT89LP51RD2/ED2/ID2 microcontroller features 64K bytes of on-chip In-System Programmable Flash program memory and 4K bytes of EEPROM data memory. In-System Pro- gramming allows programming and reprogramming of the microcontroller positioned inside the end system. The programmer communicates serially with the AT89LP51RD2/ED2/ID2 micro- controller, reprogramming all nonvolatile memories on the chip ...
Page 188
... Memory Organization The AT89LP51RD2/ED2/ID2 offers 64K bytes of In-System Programmable nonvolatile Flash code memory and 4K bytes of nonvolatile EEPROM data memory. In addition, the device con- tains a 512-byte User Signature Array, a 128-byte read-only Atmel Signature Array and 19 User Configuration Fuses. The memory organization is shown in code memory and auxiliary memories are divided into pages of 128 bytes each and share a tem- porary page buffer of 64 bytes (one half page) ...
Page 189
... User Signature Array The AT89LP51RD2/ED2/ID2 includes a 512-byte User Signature Array in four 128-byte pages. The User Signature Array is available for serial numbers, firmware revision information, date codes or other user parameters. The User Signature Array may only be written by an external ISP programmer when the User Signature Programming Fuse is enabled. When the fuse is enabled, Chip Erase will also erase the third page of the array ...
Page 190
... AT89LP51ID2 24.2 User Configuration Fuses The AT89LP51RD2/ED2/ID2 includes 19 user fuses for configuration of the device. Each fuse is accessed at a separate address in the User Fuse Row, with each byte representing one fuse as listed in code bytes except they are not affected by Chip Erase. Fuses can be cleared at any time by writ- ing 00H to the appropriate locations in the fuse row ...
Page 191
... Changes to these fuses will only take effect after the ISP session terminates by bringing RST inactive. 24.3 Flash Hardware Security The AT89LP51RD2/ED2/ID2 provides three Hardware Security Bits (or Lock Bits) for Flash Code Memory and Data EEPROM security. Security bits can be left unprogrammed (FFh) or programmed (00h) to obtain the protection levels listed in erased (set to FFh) by Chip Erase ...
Page 192
... The AT89LP51RD2/ED2/ID2 supports In-Application Programming (IAP), allowing the program memory to be modified during execution. IAP can be used to modify the user application on the fly or to use program memory for nonvolatile data storage. The AT89LP51RD2/ED2/ID2 includes a Flash Application Programming Interface (API) as part of the bootloader ROM code. ...
Page 193
... READ HSB 0Bh XXh READ BOOT ID1 0Eh XXh READ BOOT ID2 0Eh XXh READ BOOT 0Fh XXh VERSION 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary A DPTR0 DPTR1 0000h XXh 0001h XXh 0002h XXh 0003h XXh DPH = 00h DPH = 20h DPH = 40h ...
Page 194
... Get the status of the Flash memory (busy/not busy) CAUTION: The incorrect usage of these functions can make the system unstable or inoperable. For internal execution from user space the AT89LP51RD2/ED2/ID2 uses an idle-while-write architecture where the CPU is placed in an idle state while programming occurs. When the write completes, the CPU will continue executing with the instruction after the instruction that started the write sequence (usually a MOV to FCON) ...
Page 195
... Loading the Page Buffer The AT89LP51RD2/ED2/ID2 includes a temporary page buffer of 64 bytes, or one half of a page. Because the page buffer is 64 bytes long, the maximum number of bytes written at one time is 64. Therefore, two write cycles are required to fill an entire 128-byte page, one for the low half page (00H– ...
Page 196
... Launch the programming by writing the data sequence 50H followed by A0H to FCON register 4. If launched from internal memory, the CPU idles until programming completes. If launched from external memory, poll the FBUSY flag until it is cleared 5. Restore the interrupts ( AT89LP51RD2/ED2/ID2 Preliminary 196 00 Page Buffer Data Memory ...
Page 197
... If launched from internal memory, the CPU idles until programming completes. If launched from external memory, poll the FBUSY flag until it is cleared 5. Restore the interrupts ( 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary Exec: MOVX @DPTR, A Data memory Mapping FCON = 00h (FPS = 0) The last page address used when loading the page buffer is the one used to select the page pro- gramming address ...
Page 198
... The following procedure is used to read the User code space: 1. Map the code space by writing 00H to FCON (the default) 2. Read one byte in Accumulator by executing MOVC A,@A+DPTR where A+DPTR is the address of the code byte to read AT89LP51RD2/ED2/ID2 Preliminary 198 Flash Spaces Programming Page Buffer Loading ...
Page 199
... Read one byte in Accumulator by executing MOVC A,@A+DPTR where A+DPTR is 0000– 007FH for the User Fuses and 0080–00FFH for the Hardware Security • Clear FCON to unmap the User Fuses/Hardware Security Figure 24-5. Reading Procedure Note: 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary 24-5: Figure 24-5: Flash Spaces Reading Flash Spaces Mapping ...
Page 200
... The bootloader manages communication according to a specifically defined protocol to provide the whole access and service on Flash memory. Furthermore, all accesses and routines can be called from the user application. AT89LP51RD2/ED2/ID2 Preliminary 200 FPL1 FPL0 FPS ...