AT89LP51RD2 Atmel Corporation, AT89LP51RD2 Datasheet - Page 118

• Manufacturer Part Number: AT89LP51RD2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RD2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

17.4.2
Table 17-8.
Table 17-9.
17.5
118
SADDR Address = 0A9H
Not Bit Addressable
Bit
Symbol
SADDR
SADEN Address = 0B9H
Not Bit Addressable
Bit
Symbol
SADEN
More About Mode 0
7-0
7-0
AT89LP51RD2/ED2/ID2 Preliminary
Broadcast Address
7
7
Function
UART Slave Address
When SM2 = 1, SADDR holds the 8-bit address for the UART multiprocessor communication mode. This address is
combined with SADEN to create the given and broadcast addresses for the device.
Function
UART Slave Address Mask
When SM2 = 1, SADEN holds the 8-bit address mask for the UART multiprocessor communication mode. This address
is combined with SADDR to create the given and broadcast addresses for the device.
SADDR – Slave Address Register
SADEN – Slave Address Mask Register
The Broadcast Address for each slave is created by taking the logic OR of SADDR and SADEN.
Zeros in this result are trended as don’t cares. In most cases, interpreting the don’t cares as
ones, the broadcast address will be FF hexadecimal.
In Mode 0, the UART is configured as a two wire half-duplex synchronous serial interface. In
two-wire mode serial data enters and exits through RXD and TXD outputs the shift clock. Eight
data bits are transmitted/received, with the LSB first.
show simplified functional diagrams of the serial port in Mode 0 and associated timing. The baud
rate is programmable to 1/2 or 1/4 the system frequency by setting/clearing the SMOD1 bit in
Fast mode, or 1/3 or 1/6 the system frequency in Compatibility mode. However, changing
SMOD1 has an effect on the relationship between the clock and data as described below. The
baud rate can also be generated by Timer 1 by setting TB8 in SCON or the Internal Baud Rate
Generator by setting SRC in BDRCON.
Table 17-10. Mode 0 Baud Rates
6
6
SRC
0
0
0
0
1
1
TB8
5
5
0
0
1
1
X
X
SMOD1
0
1
0
1
0
1
4
4
(Timer 1 Overflow) / 4
(Timer 1 Overflow) / 2
(BRG Overflow) / 2
Baud Rate (Fast)
Table 17-10
BRG Overflow
3
3
f
f
SYS
SYS
/4
/2
lists the baud rate options for Mode 0.
Figure 17-4
2
2
Reset Value = 0000 0000B
Reset Value = 0000 0000B
and
Baud Rate (Compatibility)
1
1
(Timer 1 Overflow) / 4
(Timer 1 Overflow) / 2
Figure 17.6 on page 122
(BRG Overflow) / 2
BRG Overflow
f
f
SYS
SYS
/6
/3
3714A–MICRO–7/11
0
0