AT89LP51RD2 Atmel Corporation, AT89LP51RD2 Datasheet - Page 55

• Manufacturer Part Number: AT89LP51RD2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RD2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

7.3
3714A–MICRO–7/11
External Reset
Figure 7-3.
The AT89LP51RD2/ED2/ID2 allows for a wide V
be sufficient to prevent incorrect execution if V
range, such as when a 5.0V supply is coupled with high frequency operation. In such cases an
external Brown-out Reset circuit connected to the RST pin may be required.
The RST pin of the AT89LP51RD2/ED2/ID2 can function as either an active-low reset input or
as an active-high reset input. The polarity of the RST pin is selectable using the POL pin (for-
merly EA). When POL is high the RST pin is active high with an on-chip pull-down resistor tied to
GND. When POL is low the RST pin is active low with an on-chip pull-up resistor tied to V
RST pin structure is shown in
ence of the active reset level on the input will immediately reset the device. A glitch filter will
suppress all reset input pulses of less than 50 ns. Exit from reset is synchronous. In Compatibil-
ity mode the reset pin is sampled every six clock cycles and must be held inactive for at least
twelve clock cycles to deassert the internal reset. In Fast mode the reset pin is sampled every
clock cycle and must be held inactive for at least two clock cycles to deassert the internal reset.
The AT89LP51RD2/ED2/ID2 includes an on-chip Power-On Reset and Brown-out Detector cir-
cuit that ensures that the device is reset from system power up. In most cases a RC startup
circuit is not required on the RST pin, reducing system cost, and the RST pin may be left uncon-
nected if a board-level reset is not present.
Note:
Figure 7-4.
Time-out
WDT Reset
Internal
DISRTO
Internal Reset
Reset
V
RST also serves as the In-System Programming (ISP) enable. ISP is enabled when the external
reset pin is held active. When ISP is disabled by fuse, ISP may only be entered by pulling RST
active during power-up. If this behavior is necessary, it is recommended to use an active-low reset
so that ISP can be entered by shorting RST to GND at power-up.
DD
Brown-out Detector Reset
Reset Pin Structure
V POR
AT89LP51RD2/ED2/ID2 Preliminary
V
Figure
CC
POL = 1
7-4. Entry into reset is completely asynchronous. The pres-
RST
V BOD
t SUT
DD
BOD
WDT Reset
operating range. The on-chip BOD may not
DISRTO
Internal Reset
is lower than the minimum required V
V
CC
POL = 0
RST
DD
. The
55
DD