AT89LP51RD2 Atmel Corporation, AT89LP51RD2 Datasheet - Page 85

• Manufacturer Part Number: AT89LP51RD2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RD2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

13.6
3714A–MICRO–7/11
Pulse Width Modulation
Figure 13-4. Timer/Counter 0 Mode 3: Two 8-bit Counters
On the AT89LP51RD2/ED2/ID2, Timer 0 and Timer 1 may be independently configured as 8-bit
asymmetrical (edge-aligned) pulse width modulators (PWM) by setting the PWM0EN or
PWM1EN bits in TCONB, respectively. In PWM Mode the generated waveform is output on the
timer's input pin, T0 or T1. Therefore, C/Tx must be set to “0” when in PWM mode and the T0
(P3.4) and T1 (P3.5) must be configured in an output mode. The Timer Overflow Flags and
Interrupts will continue to function while in PWM Mode and Timer 1 may still generate the baud
rate for the UART. The timer GATE function also works in PWM mode, allowing the output to be
halted by an external input. Each PWM channel has four modes selected by the mode bits in
TMOD.
An example waveform for Timer 0 in PWM Mode 0 is shown in
counter while RH0 stores the 8-bit compare value. When TH0 is 00H the PWM output is
set high. When the TH0 count reaches the value stored in RH0 the PWM output is set low.
Therefore, the pulse width is proportional to the value in RH0. To prevent glitches, writes to
RH0 only take effect on the FFH to 00H overflow of TH0. Setting RH0 to 00H will keep the PWM
output low.
Figure 13-5. 8-bit Asymmetrical Pulse Width Modulation
(P3.4)T0
INT0 Pin
GATE0
CLK
CLK
T0 Pin
RH0
FFH
00H
SYS
SYS
TH0
÷TPS
÷TPS
AT89LP51RD2/ED2/ID2 Preliminary
C/T = 0
C/T =1
Control
Control
TF0 Set
(8 Bits)
(8 Bits)
Figure
13-5. TH0 acts as an 8-bit
Inter r up t
Inter r up t
time
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