ATmega64A Atmel Corporation, ATmega64A Datasheet - Page 252

• Manufacturer Part Number: ATmega64A
• Manufacturer: Atmel Corporation

Specifications of ATmega64A

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24. JTAG Interface and On-chip Debug System
24.1
24.2
24.3
8160C–AVR–07/09
Features
Overview
TAP – Test Access Port
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The AVR IEEE std. 1149.1 compliant JTAG interface can be used for:
A brief description is given in the following sections. Detailed descriptions for Programming via
the JTAG interface, and using the Boundary-scan chain can be found in the sections
ming Via the JTAG Interface” on page 314
259, respectively. The On-chip Debug support is considered being private JTAG instructions,
and distributed within ATMEL and to selected third party vendors only.
Figure 24-1
TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller
selects either the JTAG Instruction Register or one of several data registers as the scan chain
(Shift Register) between the TDI – input and TDO – output. The Instruction Register holds JTAG
instructions controlling the behavior of a data register.
The ID-Register, Bypass Register, and the Boundary-scan Chain are the data registers used for
board-level testing. The JTAG Programming Interface (actually consisting of several physical
and virtual data registers) is used for serial programming via the JTAG interface. The Internal
Scan Chain and Break Point Scan Chain are used for On-chip debugging only.
The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins
constitute the Test Access Port – TAP. These pins are:
• Testing PCBs by using the JTAG Boundary-scan capability.
• Programming the non-volatile memories, Fuses and Lock bits.
• On-chip debugging.
JTAG (IEEE std. 1149.1 Compliant) Interface
Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard
Debugger Access to:
Extensive On-chip Debug Support for Break Conditions, Including
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
On-chip Debugging Supported by AVR Studio
– All Internal Peripheral Units
– Internal and External RAM
– The Internal Register File
– Program Counter
– EEPROM and Flash Memories
– AVR Break Instruction
– Break on Change of Program Memory Flow
– Single Step Break
– Program Memory Break Points on Single Address or Address Range
– Data Memory Break Points on Single Address or Address Range
shows a block diagram of the JTAG interface and the On-chip Debug system. The
and
®
“IEEE 1149.1 (JTAG) Boundary-scan” on page
ATmega64A
“Program-
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