ATmega64A Atmel Corporation, ATmega64A Datasheet - Page 272

• Manufacturer Part Number: ATmega64A
• Manufacturer: Atmel Corporation

Specifications of ATmega64A

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8160C–AVR–07/09
Table 25-5.
Note:
If the ADC is not to be used during scan, the recommended input values from
be used. The user is recommended not to use the Differential Gain stages during scan. Switch-
cap based gain stages require fast operation and accurate timing which is difficult to obtain
when used in a scan chain. Details concerning operations of the differential gain stage is there-
fore not provided.
The AVR ADC is based on the analog circuitry shown in
imation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is
usually to ensure that an applied analog voltage is measured within some limits. This can easily
be done without running a successive approximation algorithm: apply the lower limit on the digi-
tal DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit
on the digital DAC[9:0] lines, and verify the output from the comparator to be high.
The ADC needs not be used for pure connectivity testing, since all analog inputs are shared with
a digital port pin as well.
When using the ADC, remember the following:
Signal
Name
SCTEST
ST
VCCREN
• The Port Pin for the ADC channel in use must be configured to be an input with pull-up
• In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when
• The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal
disabled to avoid signal contention.
enabling the ADC. The user is advised to wait at least 200 ns after enabling the ADC before
controlling/observing any ADC signal, or perform a dummy conversion before using the first
result.
low (Sample mode).
1. Incorrect setting of the switches in
the part. There are several input choices to the S&H circuitry on the negative input of the out-
put comparator in
Bandgap reference source, or Ground.
Boundary-scan Signals for the ADC
Input
Input
Direction
as Seen
from the
ADC
Input
Figure
Description
Switch-cap TEST
enable. Output from
x10 gain stage send
out to Port Pin having
ADC_4
Output of gain stages
will settle faster if this
signal is high first two
ACLK periods after
AMPEN goes high.
Selects Vcc as the
ACC reference
voltage.
25-10. Make sure only one path is selected from either one ADC pin,
Figure 25-10
(1)
Recommended
Input when not
(Continued)
will make signal contention and may damage
Figure 25-10
in Use
0
0
0
with a successive approx-
Recommended Inputs
are Used, and CPU is
ATmega64A
Output Values when
not Using the ADC
Table 25-5
0
0
0
should
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