ATmega64A Atmel Corporation, ATmega64A Datasheet - Page 273

• Manufacturer Part Number: ATmega64A
• Manufacturer: Atmel Corporation

Specifications of ATmega64A

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Table 25-6.
Note:
25.6
8160C–AVR–07/09
Ste
p
1
2
3
4
5
6
7
8
9
10
11
Actions
SAMPLE_PRELOAD
EXTEST
Verify the COMP bit scanned out to be 0
Verify the COMP bit scanned out to be 1
1. Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock frequency. As the algorithm keeps
ATmega64A Boundary-scan Order
HOLD high for five steps, the TCK clock frequency has to be at least five times the number of scan bits divided by the maxi-
mum hold time, t
Algorithm for Using the ADC
hold,max
As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when
the power supply is 5.0V and AREF is externally connected to V
The recommended values from
rithm in
“Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register
with the succeeding columns. The verification should be done on the data scanned out when
scanning in the data on the same row in the table.
Table 25-7
selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The
scan order follows the pinout order as far as possible. Therefore, the bits of Port A are scanned
in the opposite bit order of the other ports. Exceptions from the rules are the scan chains for the
analog circuits, which constitute the most significant bits of the scan chain regardless of which
physical pin they are connected to. In
.
Table
shows the Scan order between TDI and TDO when the Boundary-scan Chain is
25-6. Only the DAC and Port Pin values of the Scan-chain are shown. The column
(1)
The lower limit is:
The upper limit is:
ADCEN
1
1
1
1
1
1
1
1
1
1
1
0x200
0x200
0x200
0x123
0x123
0x200
0x200
0x200
0x143
0x143
0x200
Table 25-5
DAC
1024 1.5V 0,95 5V
Figure
1024 1.5V 1.05 5V
MUXEN
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
⋅
⋅
are used unless other values are given in the algo-
25-3, PXn, Data corresponds to FF0, PXn. Control
⋅
⋅
HOLD
1
0
1
1
1
1
0
1
1
1
1
⁄
⁄
=
PRECH
=
291
323
1
1
1
1
0
1
1
1
1
0
1
CC
=
=
.
0x123
0x143
PA3.
Data
0
0
0
0
0
0
0
0
0
0
0
ATmega64A
Control
PA3.
0
0
0
0
0
0
0
0
0
0
0
Enable
Pull-
PA3.
up_
0
0
0
0
0
0
0
0
0
0
0
273