ATtiny48 Atmel Corporation, ATtiny48 Datasheet - Page 20

• Manufacturer Part Number: ATtiny48
• Manufacturer: Atmel Corporation

Specifications of ATtiny48

• Flash (kbytes): 4 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

5.3
5.3.1
20
Data Memory (EEPROM)
ATtiny48/88
Programming Methods
Figure 5-2.
ATtiny48/88 contains 64 bytes of non-volatile data memory. This EEPROM is organized as a
separate data space, in which single bytes can be read and written. All access registers are
located in the I/O space.
The EEPROM memory layout is summarised in
Table 5-3.
The internal 8MHz oscillator is used to time EEPROM operations. The frequency of the oscillator
must be within the requirements described in
page
When powered by heavily filtered supplies, the supply voltage, V
on power-up and power-down. Slow rise and fall times may put the device in a state where it is
running at supply voltages lower than specified. To avoid problems in situations like this, see
“Preventing EEPROM Corruption” on page
The EEPROM has a minimum endurance of 100,000 write/erase cycles.
There are two methods for EEPROM programming:
Device
ATtiny48/88
• Atomic byte programming. This is the simple mode of programming, where target locations
• Split byte programming. It is possible to split the erase and write cycle in two different
are erased and written in a single operation. In this mode of operation the target is
guaranteed to always be erased before writing but programmin times are longer.
operations. This is useful when short access times are required, for example when supply
voltage is falling. In order to take advantage of this method target locations must be erased
34.
Address
clk
On-chip Data SRAM Access Cycles
Size of Non-Volatile Data Memory (EEPROM).
Data
Data
WR
CPU
RD
Compute Address
EEPROM Size
64B
T1
Memory Access Instruction
22.
“OSCCAL – Oscillator Calibration Register” on
Table
Address valid
T2
5-3, below.
Address Range
0x00 – 0x3F
CC
Next Instruction
, is likely to rise or fall slowly
T3
8008H–AVR–04/11