ATxmega128B3 Atmel Corporation, ATxmega128B3 Datasheet - Page 253

• Manufacturer Part Number: ATxmega128B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B3

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.9.5
8291A–AVR–10/11
BAUD
–
Baud Rate register
• Bit 5
This flag is set when the master is holding the SCL line low. This is a status flag and a read-only
flag that is set when RIF or WIF is set. Clearing the interrupt flags and releasing the SCL line will
indirectly clear this flag.
The flag is also cleared automatically for the same conditions as RIF.
• Bit 4
This flag contains the most recently received acknowledge bit from the slave. This is a read-only
flag. When read as zero, the most recent acknowledge bit from the slave was ACK, and when
read as one the most recent acknowledge bit was NACK.
• Bit 3
This flag is set if arbitration is lost while transmitting a high data bit or a NACK bit, or while issu-
ing a START or repeated START condition on the bus. Writing a one to this bit location will clear
ARBLOST.
Writing the ADDR register will automatically clear ARBLOST.
• Bit 2
This flag is set if an illegal bus condition has occurred. An illegal bus condition occurs if a
repeated START or a STOP condition is detected, and the number of received or transmitted
bits from the previous START condition is not a multiple of nine. Writing a one to this bit location
will clear BUSERR.
Writing the ADDR register will automatically clear BUSERR.
• Bit 1:0
These bits indicate the current TWI bus state as defined in
is dependent on bus activity. Refer to the
Table 19-6.
Writing 01 to the BUSSTATE bits forces the bus state logic into the idle state. The bus state logic
cannot be forced into any other state. When the master is disabled, and after reset, the bus state
logic is disabled and the bus state is unknown.
Bit
+0x04
Read/Write
Initial Value
BUSSTATE[1:0]
–
–
–
–
–
CLKHOLD: Clock Hold
RXACK: Received Acknowledge
ARBLOST: Arbitration Lost
BUSERR: Bus Error
00
01
10
11
BUSSTATE[1:0]: Bus State
R/W
7
0
TWI master bus state.
R/W
6
0
UNKNOWN
IDLE
OWNER
BUSY
Group Configuration
R/W
5
0
Section 19.4 ”TWI Bus State Logic” on page
R/W
4
0
BAUD[7:0]
R/W
Description
Unknown bus state
Idle bus state
Owner bus state
Busy bus state
3
0
Atmel AVR XMEGA B
Table
R/W
2
0
19-6. The change of bus state
R/W
1
0
R/W
0
0
243.
BAUD
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