ATxmega128B3 Atmel Corporation, ATxmega128B3 Datasheet - Page 55

• Manufacturer Part Number: ATxmega128B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B3

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.13.2
5.13.3
8291A–AVR–10/11
INTFLAGS – Interrupt Status Register
STATUS – Status Register
• Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to one when this register is written.
• Bit 5:4 – CHnERRIF[1:0]: Channel n Error Interrupt Flag
If an error condition is detected on DMA channel n, the CHnERRIF flag will be set. Writing a one
to this bit location will clear the flag.
• Bit 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to one when this register is written.
• Bit 1:0 – CHnTRNFIF[1:0]: Channel n Transaction Complete Interrupt Flag
When a transaction on channel n has been completed, the CHnTRFIF flag will be set. If unlim-
ited repeat count is enabled, this flag is read as one after each block transfer. Writing a one to
this bit location will clear the flag.
• Bit 7:6 – Reserved
These bits are unused and reserved for future use.
• Bit 5:4 – CHnBUSY[1:0]: Channel n Busy
When channel n starts a DMA transaction, the CHnBUSY flag will be read as one. This flag is
automatically cleared when the DMA channel is disabled, when the channel n transaction com-
plete interrupt flag is set, or if the DMA channel n error interrupt flag is set.
• Bit 3:2 – Reserved
These bits are unused and reserved for future use.
• Bit 1:0 – CHnPEND[1:0]: Channel n Pending
If a block transfer is pending on DMA channel n, the CHnPEND flag will be read as one. This
flag is automatically cleared when the block transfer starts or if the transfer is aborted.
Bit
+0x03
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
R
7
–
0
7
–
R
0
R
6
–
0
R
6
–
0
CH1ERRIF
R/W
CH1BUSY
5
0
R
5
0
CH0ERRIF
R/W
CH0BUSY
4
0
R
4
0
R
3
–
0
R
3
–
0
Atmel AVR XMEGA B
R
2
–
0
R
2
–
0
CH1TRNFIF
CH1PEND
R/W
1
0
R
1
0
CH0TRNFIF
CH0PEND
R/W
0
0
R
0
0
INTFLAGS
STATUS
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