ATxmega192A3 Atmel Corporation, ATxmega192A3 Datasheet - Page 351

• Manufacturer Part Number: ATxmega192A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega192A3

• Flash (kbytes): 192 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.4.4
29.4.4.1
29.4.5
8077H–AVR–12/09
Frame Format and Characters
Serial transmission and reception
Special data characters
The JTAG physical layer supports a fixed frame format. A serial frame is defined to be one char-
acter of eight data bits followed by one parity bit.
Figure 29-10. JTAG serial frame format
Table 29-2.
Three data characters are given a special meaning. Common for all three characters is that the
Parity bit is inverted in order to force parity error upon reception. The BREAK character
(0xBB+P1) is used by the External Programmer to force the PDI to abort any on-going operation
and bring the PDI Controller into a known state. The DELAY Character (0xDB+P1) is used by
the PDI to tell the programmer that it has no data ready programmer that it has no transmission
pending (i.e. the PDI is in RX-mode).
Figure 29-11. Special data characters
The JTAG interface supports full duplex communication. At the same time as input data is
shifted in on the TDI pin, output data is shifted out on the TDO pin. However, PDI communica-
tion relies on half duplex data transfer. Dictated by the PDI Controller, the JTAG physical layer
operates in either Transmit- (TX) or Receive- (RX) mode. The available JTAG bit channel is
used for control and status signalling.
The programmer and the JTAG interface operate synchronously on the TCK clock provided by
the programmer. The dependency between the clock edges and data sampling or data change
is fixed. As illustrated in
the falling edge of TCK, while data always should be sampled on the rising edge of TCK.
(0-7)
P
Data/command bits, least significant bit sent first (0 to 7)
Parity bit, even parity is used
Figure 29-10 on page
1
1
1
0
1
1
1
1 EMPTY CHARACTER (EB+P1)
1 BREAK CHARACTER (BB+P1)
1 DELAY CHARACTER (DB+P1)
1
0
0
0
2
1
1
1
3
351, TDI and TDO is always set up (changed) on
1
1
0
FRAME
4
1
0
1
5
0
1
1
6
1
1
1
7
P1
P1
P1
P
XMEGA A
351