ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 126

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ATxmega64A1

Manufacturer Part Number
ATxmega64A1
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega64A1

Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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12.6.2
8077H–AVR–12/09
Round-robin scheduling
Figure 12-1. Static priority.
To avoid the possible starvation problem for low level interrupts with static priority, the PMIC
gives the possibility for round-robin scheduling for low level interrupts. When round-robin sched-
uling is enabled, the interrupt vector address for the last acknowledged low level interrupt will
have the lowest priority next time one or more interrupts from the low level is requested.
Figure 12-2. Round-robin scheduling.
IV EC x las t ack now le dge d
inte rrupt
IV EC x+1
IV EC N
IV EC 0
IV EC x
:
:
:
:
:
:
Lowes t Addres s
Highes t Addres s
Low est Priority
Highest Priority
IVEC x+1
IVEC N
IVEC 0
IVEC x
:
:
:
:
:
:
IV EC x+1 las t ack now le dge d
inte rrupt
IV EC x+1
IV EC x+2
IV EC N
IV EC 0
IV EC x
Highes t Priority
Lowes t Priority
:
:
:
:
:
:
Low est Priority
Highest Priority
XMEGA A
126

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