ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 383

• Manufacturer Part Number: ATxmega64A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A1

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.12.3.1
30.12.3.2
30.12.3.3
30.12.3.4
30.12.3.5
8077H–AVR–12/09
Chip Erase
Read NVM
Erase Page Buffer
Load Page Buffer
Erase Page
The Chip Erase command is used to erase the Flash Program Memory, EEPROM and Lock
Bits. Erasing of the EEPROM depend EESAVE fuse setting, refer to
tile Memory Fuse Byte 5” on page 32
Fuses are not effected.
Once this operation starts the PDIBUS between the PDI controller and the NVM is disabled, and
the NVMEN bit in the PDI STATUS register is cleared until the operation is finished. Poll the
NVMEN bit until this is set again, indicting the PDIBUS is enabled.
The BUSY flag in the NVM STATUS register will be set until the operation is finished.
The Read NVM command is used to read the Flash, EEPROM, Fuses, and Signature and Cali-
bration row sections.
Dedicated Read EEPROM, Read Fuse and Read Signature Row and Read Calibration Row
commands are also available for the various memory sections. The algorithm for these com-
mands are the same as for the NVM Read command.
The Erase Flash Page Buffer and Erase EEPROM Page Buffer commands are used to erase
the Flash and EEPROM page buffers.
The BUSY flag in the NVM STATUS register will be set until the operation is completed.
The Load Flash Page Buffer and Load EEPROM Page Buffer commands are used to load one
byte of data into the Flash and EEPROM page buffers.
Since the Flash page buffer is word accessing and the PDI uses byte addressing, the PDI must
write the Flash Page Buffer in correct order. For the write operation, the low-byte of the word
location must be written before the high-byte. The low-byte is then written into the temporary
register. The PDI then writes the high-byte of the word location, and the low-byte is then written
into the word location page buffer in the same clock cycle.
The PDI interface is automatically halted, before the next PDI instruction can be executed.
The Erase Application Section Page, Erase Boot Loader Section Page, Erase User Signature
Row and Erase EEPROM Page commands are used to erase one page in the selected memory
space.
1. Load the NVM CMD register with Chip Erase command.
2. Set the CMDEX bit in NVM CTRLA register. This requires the timed CCP sequence
1. Load the NVM CMD register with the Read NVM command.
2. Read the selected memory address by doing a PDI Read operation.
1. Load the NVM CMD register with the Erase Flash/EEPROM Page Buffer command.
2. Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence
1. Load the NVM CMD register with the Load Flash/EEPROM Page Buffer command.
2. Write the selected memory address by doing a PDI Write operation.
during self-programming.
during self-programming.
for details. The User Signature Row, Calibration Row and
”FUSEBYTE5 - Non-Vola-
XMEGA A
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