ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 53

• Manufacturer Part Number: ATxmega64A1
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A1

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 78
• Ext Interrupts: 78
• Usb Speed: No
• Usb Interface: No
• Spi: 12
• Twi (i2c): 4
• Uart: 8
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 8
• Output Compare Channels: 24
• Input Capture Channels: 24
• Pwm Channels: 24
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.13
5.13.1
8077H–AVR–12/09
Register Description – DMA Controller
CTRL - DMA Control Register
• Bit 7 - ENABLE: DMA Enable
Setting this bit enables the DMA Controller. If the DMA Controller is enabled and this bit is writ-
ten to zero, the ENABLE bit is not cleared before the internal transfer buffer is empty and the
DMA data transfer is aborted.
• Bit 6 - RESET: DMA Software Reset
Setting this bit enables the software reset. This bit is automatically cleared when reset is com-
pleted. This bit can only be set when the DMA Controller is disabled (ENABLE = 0).
• Bit 5:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:2 - DBUFMODE[1:0]: DMA Double Buffer Mode
These bits enables the double buffer on the different channels according to
Table 5-1.
• Bit 1:0 - PRIMODE[1:0]: DMA Channel Priority Mode
These bits determine the internal channel priority according to
Table 5-2.
Bit
+0x00
Read/Write
Initial Value
DBUFMODE[1:0]
PRIMODE[1:0]
00
01
10
11
00
01
10
11
ENABLE
R/W
DMA Double Buffer settings
DMA Channel Priority settings
7
0
Group Configuration
Group Configuration
RESET
R/W
6
0
CH0RR123
CH01RR23
CH01CH23
DISABLED
RR0123
CH0123
CH01
CH23
R
5
0
-
4
R
0
-
Description
Round Robin
Channel0 > Round Robin (Channel 1, 2 and 3)
Channel0 > Channel1 > Round Robin (Channel 2 and
3)
Channel0 > Channel1 > Channel2 > Channel3
Description
No double buffer enabled
Double buffer enabled on channel0/1
Double buffer enabled on channel2/3
Double buffer enabled on channel0/1 and channel2/3
R/W
DBUFMODE[1:0]
3
0
R/W
2
0
Table
5-2.
R/W
1
0
PRIMODE[1:0]
Table
XMEGA A
R/W
0
0
5-1.
CTRL
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