ATxmega64A3 Atmel Corporation, ATxmega64A3 Datasheet - Page 238

• Manufacturer Part Number: ATxmega64A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Table 21-1.
Note:
21.3.2
21.3.3
8077H–AVR–12/09
Operating Mode
Asynchronous Normal
Speed mode (CLK2X = 0)
Asynchronous Double
Speed mode (CLK2X = 1)
Synchronous and SPI
Master mode
1. The baud rate is defined to be the transfer rate in bit per second (bps)
External Clock
Double Speed Operation (CLK2X)
Equations for Calculating Baud Rate Register Setting
External clock is used in synchronous slave mode operation. The XCK clock input is sampled on
the Peripheral Clock frequency (f
meta-stability. The output from the synchronization register is then passed through an edge
detector. This process introduces a delay of two peripheral clock periods, and therefore the max-
imum external XCK clock frequency (f
Each high and low period the XCK clock cycles must be sampled twice by the Peripheral Clock.
If the XCK clock has jitter, or the high/low period duty cycle is not 50/50, the maximum XCK
clock speed must be reduced accordingly.
Double Speed operation can be enabled to allow for higher baud rates on lower peripheral clock
frequencies under asynchronous operation. When Double Speed operation is enabled the baud
rate for a given asynchronous baud rate setting as shown in
bled. In this mode the Receiver will use half the number of samples (reduced from 16 to 8) for
data sampling and clock recovery. Due to the reduced sampling more accurate baud rate setting
and peripheral clock are required. See
243
f
XCK
Conditions
BSCALE ≥ 0
BSCALE < 0
BSCALE ≥ 0
BSCALE < 0
f
f
f
f
f
BAUD
BAUD
BAUD
BAUD
BAUD
for more details on accuracy.
<
f
---------- -
PER
4
≤
≤
≤
≤
<
f
---------- -
f
---------- -
f
---------- -
f
---------- -
f
---------- -
PER
PER
PER
PER
PER
16
16
8
8
2
f
f
BAUD
BAUD
f
f
BAUD
BAUD
Equation for Calculation
PER
=
=
f
=
BAUD
=
------------------------------------------------------------------ -
16((2
--------------------------------------------------------------- -
8((2
) by a synchronization register to minimize the chance of
XCK
Baud Rate
-------------------------------------------------------------- -
2
------------------------------------------------------------- -
2
BSCALE
BSCALE
Section 21.8 ”Asynchronous Data Reception” on page
BSCALE
)is limited by the following equation:
=
BSCALE
------------------------------------ -
2
⋅
⋅
f
(
⋅
f
PER
f
8
BSEL
f
PER
16(
PER
⋅
PER
(1)
f
⋅
⋅
PER
BSEL )
(
BSEL )
BSEL
BSEL
+
1
+
)
+
+
+
1)
1
1)
1)
)
Table 21-1 on page 238
BSEL
BSEL
BSEL
BSEL
Equation for Calculation
BSEL
=
=
=
=
---------------------
2
------------------------------------------------ 1
2
BSEL Value
---------------------
2
-------------------------------------------- - 1
2
BSCALE
BSCALE
BSCALE
BSCALE
1
=
1
XMEGA A
------------------ - 1
2f
f
f
f
BAUD
PER
PER
PER
⎛
⎝
⋅
⎛
⎝
--------------------- - 1
16f
⋅ f
16
------------------ - 1
8f
8
f
f
BAUD
PER
PER
f
BAUD
BAUD
will be dou-
BAUD
–
–
–
–
–
⎞
⎠
⎞
⎠
238