ATxmega64A3 Atmel Corporation, ATxmega64A3 Datasheet - Page 252

• Manufacturer Part Number: ATxmega64A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21.15.5
8077H–AVR–12/09
CTRLC - USART Control Register C
• Bit 3 - TXEN: Transmitter Enable
Setting this bit enables the USART Transmitter. The Transmitter will override normal port opera-
tion for the TxD pin when enabled. Disabling the Transmitter (writing TXEN to zero) will not
become effective until ongoing and pending transmissions are completed, i.e., when the Trans-
mit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When
disabled, the Transmitter will no longer override the TxD port.
• Bit 2 - CLK2X: Double Transmission Speed
Setting this bit will reduce the divisor of the baud rate divider from16 to 8 effectively doubling the
transfer rate for asynchronous communication modes. For synchronous operation this bit has no
effect and should always be written to zero. This bit must be zero when the USART Communica-
tion Mode is configured to IRCOM.
This bit is unused in Master SPI mode of operation.
• Bit 1 - MPCM: Multi-processor Communication Mode
This bit enables the Multi-processor Communication mode. When the MPCM bit is written to
one, the USART Receiver ignores all the incoming frames that do not contain address informa-
tion. The Transmitter is unaffected by the MPCM setting. For more detailed information see
”Multi-processor Communication Mode” on page
This bit is unused in Master SPI mode of operation.
• Bit 0 - TXB8: Transmit Bit 8
TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. When used this bit must be written before writing the low bits to DATA.
This bit is unused in Master SPI mode of operation.
Note:
• Bits 7:6 - CMODE[1:0]: USART Communication Mode
These bits select the mode of operation of the USART as shown in
Table 21-6.
Notes:
Bit
+0x05
+0x05
Read/Write
Initial Value
(1)
CMODE[1:0]
1. Master SPI mode
1. See
00
01
10
11
using IRCOM mode.
7
CMODE bit settings
R/W
Section 22. ”IRCOM - IR Communication Module” on page 256
0
CMODE[1:0]
CMODE[1:0]
6
Group Configuration
R/W
ASYNCHRONOUS
0
SYNCHRONOUS
IRCOM
MSPI
5
R/W
0
-
PMODE[1:0]
4
R/W
Mode
Asynchronous USART
Synchronous USART
IRCOM
Master SPI
0
-
248.
(1)
3
SBMODE
R/W
(2)
0
-
2
UDORD
Table
R/W
1
for full description on
21-6.
1
CHSIZE[2:0]
XMEGA A
UCPHA
R/W
1
0
R/W
0
-
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