Manufacturer Part NumberSAM4S16C
ManufacturerAtmel Corporation
SAM4S16C datasheets

Specifications of SAM4S16C

Flash (kbytes)1024 KbytesPin Count100
# Of Touch Channels32Hardware Qtouch AcquisitionNo
Max I/o Pins79Ext Interrupts79
Usb Transceiver1Quadrature Decoder Channels2
Usb SpeedFull SpeedUsb InterfaceDevice
Spi3Twi (i2c)2
Sd / Emmc1Graphic LcdNo
Video DecoderNoCamera InterfaceNo
Adc Channels16Adc Resolution (bits)12
Adc Speed (ksps)1000Analog Comparators1
Resistive Touch ScreenNoDac Channels2
Dac Resolution (bits)12Temp. SensorYes
Crypto EngineNoSram (kbytes)128
Self Program MemoryYESExternal Bus Interface1
Dram MemoryNoNand InterfaceYes
PicopowerNoTemp. Range (deg C)-40 to 85
I/o Supply Class1.8/3.3Operating Voltage (vcc)1.62 to 3.6
FpuNoMpu / MmuYes / No
Timers6Output Compare Channels6
Input Capture Channels6Pwm Channels4
32khz RtcYesCalibrated Rc OscillatorYes
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Download datasheet (2Mb)Embed
-M4 running at up to 120 MHz
– Memory Protection Unit (MPU)
– DSP Instruction Set
– Thumb
-2 instruction set
Pin-to-pin compatible with SAM3N, SAM3S products (48-, 64- and 100- pin versions)
and SAM7S legacy products (64-pin version)
– Up to 1024 Kbytes embedded Flash
– Up to 128 Kbytes embedded SRAM
– 16 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP routines
– 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash
– Embedded voltage regulator for single supply operation
– Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation
– Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure
Detection and optional low-power 32.768 kHz for RTC or device clock
– RTC with Gregorian and Persian Calendar mode, waveform generation in low-
power modes
– RTC clock calibration circuitry for 32.768 kHz crystal frequency compensation
– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default
frequency for device startup. In-application trimming access for frequency
– Slow Clock Internal RC oscillator as permanent low-power mode device clock
– Two PLLs up to 240 MHz for device clock and for USB
– Temperature Sensor
– Up to 24 Peripheral DMA (PDC) Channels
Low Power Modes
– Sleep and Backup modes, down to 3 µA in Backup mode
– Ultra low-power RTC
– USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints. On-Chip
– Up to 2 USARTs with ISO7816, IrDA
– Two 2-wire UARTs
– Up to 2 Two Wire Interface (I2C compatible), 1 SPI, 1 Serial Synchronous Controller
(I2S), 1 High Speed Multimedia Card Interface (SDIO/SD Card/MMC)
– 2 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and PWM
mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper
– 4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time
Generator Counter for Motor Control
– 32-bit Real-time Timer and RTC with calendar and alarm features
– Up to 16-channel, 1Msps ADC with differential input mode and programmable gain
stage and auto calibration
– One 2-channel 12-bit 1Msps DAC
– One Analog Comparator with flexible input selection, Selectable input hysteresis
– 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
– Up to 79 I/O lines with external interrupt capability (edge or level sensitivity),
debouncing, glitch filtering and on-die Series Resistor Termination
– Three 32-bit Parallel Input/Output Controllers, Peripheral DMA assisted Parallel
Capture Mode
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm
– 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-pad QFN 9x9 mm, pitch 0.5 mm
– 48-lead LQFP, 7 x 7 mm, pitch 0.5 mm/48-pad QFN 7x7 mm, pitch 0.5 mm
, RS-485, SPI, Manchester and Modem Mode
Flash MCU
SAM4S Series
NOTE: This is a summary document.
The complete document is currently not
available. For more information, please
contact your local Atmel sales office.

SAM4S16C Summary of contents

  • Page 1

    Features • Core ® ® – ARM Cortex -M4 running 120 MHz – Memory Protection Unit (MPU) – DSP Instruction Set ® – Thumb -2 instruction set • Pin-to-pin compatible with SAM3N, SAM3S products (48-, 64- and ...

  • Page 2

    ... SAM7S legacy series (64-pin versions). 1.1 Configuration Summary The SAM4S series devices differ in memory size, package and features. the configurations of the device family. Table 1-1. Configuration Summary Device Flash SRAM 1024 128 SAM4S16C Kbytes Kbytes 1024 128 SAM4S16B Kbytes Kbytes 1024 128 SAM4S16A Kbytes ...

  • Page 3

    Block Diagram Figure 2-1. SAM4S Series100-pin version Block Diagram System Controller TST PCK0-PCK2 PLLA PMC PLLB RC Osc 12/8/4 MHz XIN 3-20 MHz XOUT Osc SUPC XIN32 Osc 32 kHz XOUT32 RC 32 kHz ERASE 8 GPBREG VDDIO VDDCORE ...

  • Page 4

    Figure 2-2. SAM4S Series 64-pin version Block Diagram System Controller TST PCK0-PCK2 PLLA PLLB RC Osc 12/8/4 MHz XIN 3-20 MHz XOUT Osc SUPC XIN32 Osc 32 kHz XOUT32 RC 32 kHz ERASE 8 GPBREG VDDIO VDDCORE RTT VDDPLL POR ...

  • Page 5

    Figure 2-3. SAM4S Series 48-pin version Block Diagram System Controller TST PCK0-PCK2 PLLA PLLB RC Osc 12/8/4 MHz XIN 3-20 MHz XOUT SUPC XIN32 Osc 32 kHz XOUT32 RC 32 kHz ERASE 8 GPBREG VDDIO VDDCORE VDDPLL RTCOUT0 RTCOUT1 RSTC ...

  • Page 6

    Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function Peripherals I/O Lines and USB transceiver VDDIO Power Supply Voltage Regulator Input, ADC, DAC and VDDIN Analog Comparator Power Supply VDDOUT Voltage Regulator Output VDDPLL Oscillator and ...

  • Page 7

    Table 3-1. Signal Description List (Continued) Signal Name Function Flash and NVM Configuration Bits Erase ERASE Command NRST Synchronous Microcontroller Reset TST Test Select URXDx UART Receive Data UTXDx UART Transmit Data PA0 - PA31 Parallel IO Controller A PB0 ...

  • Page 8

    Table 3-1. Signal Description List (Continued) Signal Name Function Universal Synchronous Asynchronous Receiver Transmitter USARTx SCKx USARTx Serial Clock TXDx USARTx Transmit Data RXDx USARTx Receive Data RTSx USARTx Request To Send CTSx USARTx Clear To Send DTR1 USART1 Data ...

  • Page 9

    Table 3-1. Signal Description List (Continued) Signal Name Function TWDx TWIx Two-wire Serial Data TWCKx TWIx Two-wire Serial Clock ADC, DAC and Analog Comparator ADVREF Reference AD0-AD14 Analog Inputs ADTRG ADC Trigger DAC0 - DAC1 Analog output DACTRG DAC Trigger ...

  • Page 10

    Package and Pinout SAM4S devices are pin-to-pin compatible with SAM3N, SAM3S products in 48-, 64- and 100-pin versions, and AT91SAM7S legacy products in 64-pin versions. 4.1 SAM4S16/S8C Package and Pinout 4.1.1 100-Lead LQFP Package Outline Figure 4-1. 4.1.2 100-ball ...

  • Page 11

    LQFP Pinout Table 4-1. SAM4S16/S8C 100-lead LQFP pinout 1 ADVREF 2 GND 3 PB0/AD4 4 PC29/AD13 5 PB1/AD5 6 PC30/AD14 7 PB2/AD6 8 PC31 9 PB3/AD7 10 VDDIN 11 VDDOUT PA17/PGMD5/ 12 AD0 13 PC26 PA18/PGMD6/ 14 AD1 ...

  • Page 12

    TFBGA Pinout Table 4-2. SAM4S16/S8C 100-ball TFBGA pinout A1 PB1/AD5 C6 A2 PC29 C7 A3 VDDIO C8 A4 PB9/PGMCK/XIN C9 A5 PB8/XOUT C10 A6 PB13/DAC0 D1 A7 DDP/PB11 D2 A8 DDM/PB10 D3 A9 TMS/SWDIO/PB6 D4 A10 JTAGSEL D5 ...

  • Page 13

    SAM4S16/S8B Package and Pinout 4.2.1 64-Lead LQFP Package Outline Figure 4-3. 4.2.2 64-lead QFN Package Outline Figure 4-4. 11100AS–ATARM–27-Oct-11 Orientation of the 64-lead LQFP Package Orientation of the 64-lead QFN Package ...

  • Page 14

    LQFP and QFN Pinout Table 4-3. 64-pin SAM4S16/S8B pinout 1 ADVREF 17 2 GND 18 3 PB0/AD4 19 4 PB1/AD5 20 5 PB2/AD6 21 6 PB3/AD7 22 7 VDDIN 23 8 VDDOUT 24 PA17/PGMD5 AD0 PA18/PGMD6/ ...

  • Page 15

    SAM4S16/S8A Package and Pinout 4.3.1 48-Lead LQFP Package Outline Figure 4-5. 4.3.2 48-lead QFN Package Outline Figure 4-6. 11100AS–ATARM–27-Oct-11 Orientation of the 48-lead LQFP Package Orientation of the 48-lead QFN Package ...

  • Page 16

    LQFP and QFN Pinout Table 4-4. 48-pin SAM4S16/S8A pinout 1 ADVREF 13 2 GND 14 3 PB0/AD4 15 4 PB1/AD5 16 5 PB2/AD6 17 6 PB3/AD7 18 7 VDDIN 19 8 VDDOUT 20 PA17/PGMD5 AD0 PA18/PGMD6/ ...

  • Page 17

    Power Considerations 5.1 Power Supplies The SAM4S has several types of power supply pins: • VDDCORE pins: Power the core, the embedded memories and the peripherals. Voltage ranges from 1.08V to 1.32V. • VDDIO pins: Power the Peripherals I/O ...

  • Page 18

    Figure 5-1. Note: Figure 5-2. Note: Figure 5-3 Since the PIO state is preserved when in backup mode, any free PIO line can be used to switch off the external regulator by driving the PIO line at low level (PIO ...

  • Page 19

    Figure 5-3. 5.4 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The power management controller can be used to adapt the frequency ...

  • Page 20

    Supply Monitor alarm • RTC alarm • RTT alarm 5.5.2 Wait Mode The purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a powered state for a startup time of ...

  • Page 21

    Low Power Mode Summary Table The modes detailed above are the main low-power modes. Each part can be set off sep- arately and wake up sources can be individually configured. of the configurations of the low-power ...

  • Page 22

    Wake-up Sources The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they ...

  • Page 23

    Fast Startup The SAM4S allows the processor to restart in a few microseconds while the processor is in wait mode or in sleep mode. A fast start up can occur upon detection of a low level on one of ...

  • Page 24

    Input/Output Lines The SAM4S has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be ...

  • Page 25

    Table 6-1. System I/O Configuration Pin List. SYSTEM_IO Default function bit number after reset 12 ERASE 10 DDM 11 DDP 7 TCK/SWCLK 6 TMS/SWDIO 5 TDO/TRACESWO 4 TDI - PA7 - PA8 - PB9 - PB8 Notes PB12 ...

  • Page 26

    Test Pin The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM4S series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it ...

  • Page 27

    Processor and Architecture 7.1 ARM Cortex-M4 Processor • Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit • Harvard processor architecture enabling simultaneous instruction fetch with data load/store • Three-stage pipeline • Saturating arithmetic for signal ...

  • Page 28

    Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the Cortex-M4 S Bus to the Internal ROM. Thus, these paths are forbidden or ...

  • Page 29

    Table 7-4. Instance name PIOA TWI1 TWI0 UART1 UART0 USART1 USART0 ADC SSC HSMCI 7.7 Debug and Test Features • Debug access to all memory and registers in the system, including Cortex-M4 register bank when the core is running, halted, ...

  • Page 30

    Product Mapping Figure 8-1. SAM4S Product Mapping Code 0x00000000 Boot Memory 0x00400000 Internal Flash 0x00800000 Internal ROM 0x00C00000 Reserved 0x1FFFFFFF External RAM 0x60000000 SMC Chip Select 0 0x61000000 SMC Chip Select 1 0x62000000 SMC Chip Select 2 0x63000000 SMC ...

  • Page 31

    Memories 9.1 Embedded Memories 9.1.1 Internal SRAM The SAM4S16 device (1024 Kbytes) embeds a total of 128-Kbytes high-speed SRAM. The SAM4S8 device (512 Kbytes) embeds a total of 128-Kbytes high-speed SRAM. The SRAM is accessible over System Cortex-M4 bus ...

  • Page 32

    For sector 0: • The smaller sector 0 has 16 pages of 512Bytes • The smaller sector 1 has 16 pages of 512 Bytes • The larger sector has 96 pages of 512 Bytes From Sector The ...

  • Page 33

    Figure 9-3. Erasing the memory can be performed as follows: • 512-byte page inside a sector Bytes • 4-Kbyte Block inside a sector of 8 KBytes/48 Kbytes/64 KBytes • sector of 8 ...

  • Page 34

    Lock Regions Several lock bits are used to protect write and erase operations on lock regions. A lock region is composed of several consecutive pages, and each lock region has its associated lock bit. Table 9- locked-region’s ...

  • Page 35

    The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. SAM-BA Boot The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the on-chip Flash memory. The SAM-BA ...

  • Page 36

    Programmable Data Float Time per Chip Select • External Wait Request • Automatic Switch to Slow Clock Mode • Asynchronous Read in Page Mode Supported: Page Size Ranges from Bytes • NAND Flash additional logic supporting ...

  • Page 37

    Figure 10-1. System Controller Block Diagram VDDIO Zero-Power Power-on Reset Supply Monitor (Backup) WKUP0 - WKUP15 General Purpose Backup Registers SLCK SLCK XIN32 Xtal 32 kHz Oscillator XOUT32 Embedded 32 kHz RC Oscillator Backup Power Supply NRST FSTT0 - FSTT15 ...

  • Page 38

    System Controller and Peripheral Mapping Refer to All the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 Power-on-Reset, Brownout and Supply Monitor The SAM4S embeds three features to monitor, warn ...

  • Page 39

    The reset circuitry is based on a zero-power power-on reset cell and a brownout detector cell. The zero-power power-on reset allows the Supply Controller to start properly, while the soft- ware-programmable brownout detector allows detection of either a battery discharge ...

  • Page 40

    Figure 10-2. Clock Generator Block Diagram 10.6 Power Management Controller The Power Management Controller provides all the clock signals to the system. It provides: • the Processor Clock, HCLK • the Free running processor clock, FCLK • the Cortex SysTick ...

  • Page 41

    Figure 10-3. Power Management Controller Block Diagram The SysTick calibration value is fixed at 12500, which allows the generation of a time base with SysTick clock at 12.5 MHz (max HCLK/8 = 100 MHz/8 = 12500, so ...

  • Page 42

    ... Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead. 10.13 Chip Identification • Chip Identifier (CHIPID) registers permit recognition of the device and its revision. Table 10-1. SAM4S Chip IDs Register Chip Name SAM4S16A SAM4S16B SAM4S16C SAM4S8A SAM4S8B SAM4S8C • JTAG ID: 05B3_203F 42 Controller restoration between interrupts. Flash Size ...

  • Page 43

    UART • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun ...

  • Page 44

    Peripheral Identifiers Table 10-3 the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and control of the peripheral clock with the Power Management Controller. Table 10-3. Peripheral Identifiers Instance ID Instance Name 0 SUPC 1 RSTC ...

  • Page 45

    Table 10-3. Peripheral Identifiers (Continued) Instance ID Instance Name 32 CRCCU 33 ACC 34 UDP 10.17 Peripheral Signal Multiplexing on I/O Lines The SAM4S features 2 PIO controllers on 48-pin, 64-pin versions (PIOA and PIOB PIO controllers on ...

  • Page 46

    PIO Controller A Multiplexing Table 10-4. Multiplexing on PIO Controller A (PIOA) I/O Line Peripheral A Peripheral B PA0 PWMH0 TIOA0 PA1 PWMH1 TIOB0 PA2 PWMH2 SCK0 PA3 TWD0 NPCS3 PA4 TWCK0 TCLK0 PA5 RXD0 NPCS3 PA6 TXD0 PCK0 ...

  • Page 47

    PIO Controller B Multiplexing Table 10-5. Multiplexing on PIO Controller B (PIOB) I/O Line Peripheral A Peripheral B PB0 PWMH0 PB1 PWMH1 PB2 URXD1 NPCS2 PB3 UTXD1 PCK2 PB4 TWD1 PWMH2 PB5 TWCK1 PWML0 PB6 PB7 PB8 PB9 PB10 ...

  • Page 48

    PIO Controller C Multiplexing. Table 10-6. Multiplexing on PIO Controller C (PIOC) I/O Line Peripheral A PC0 D0 PC1 D1 PC2 D2 PC3 D3 PC4 D4 PC5 D5 PC6 D6 PC7 D7 PC8 NWE PC9 NANDOE PC10 NANDWE PC11 ...

  • Page 49

    Embedded Peripherals Overview 11.1 Serial Peripheral Interface (SPI) • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with – Serial memories, such as DataFlash – Serial peripherals, such ...

  • Page 50

    USART • Programmable Baud Rate Generator • 9-bit full-duplex synchronous or asynchronous serial communications – stop bits in Asynchronous Mode stop bits in Synchronous Mode – Parity generation and ...

  • Page 51

    Interval Measurement – Pulse Generation – Delay Timing – Pulse Width Modulation – Up/down Capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Two ...

  • Page 52

    One programmable Fault Input providing an asynchronous protection of outputs • Stepper motor control (2 Channels) 11.8 High Speed Multimedia Card Interface (HSMCI) • 4-bit or 1-bit Interface • Compatibility with MultiMedia Card Specification Version 4.3 • Compatibility with ...

  • Page 53

    Single ended/differential conversion • Programmable gain 11.11 Digital-to-Analog Converter (DAC) • channel 12-bit DAC • mega-samples conversion rate in single channel mode • Flexible conversion range • Multiple trigger sources ...

  • Page 54

    Temperature Sensor – ADVREF – AD0 to AD3 ADC channels • Plus input selection: – All analog inputs • output selection: – Internal signal – external pin – selectable inverter • window function • Interrupt on: – Rising edge, ...

  • Page 55

    Package Drawings The SAM4S series devices are available in LQFP, QFN and TFBGA packages. Figure 12-1. 100-lead LQFP Package Mechanical Drawing Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information. ...

  • Page 56

    Figure 12-2. 100-ball TFBGA Package Mechanical Drawing 56 11100AS–ATARM–27-Oct-11 ...

  • Page 57

    Figure 12-3. 64-lead LQFP Package Mechanical Drawing 11100AS–ATARM–27-Oct-11 57 ...

  • Page 58

    Figure 12-4. 64-lead QFN Package Mechanical Drawing 58 11100AS–ATARM–27-Oct-11 ...

  • Page 59

    Figure 12-5. 48-lead LQFP Package Mechanical Drawing 11100AS–ATARM–27-Oct-11 59 ...

  • Page 60

    Figure 12-6. 48-lead QFN Package Mechanical Drawing 60 11100AS–ATARM–27-Oct-11 ...

  • Page 61

    ... Ordering Information Table 13-1. Ordering Codes for SAM4S Devices Ordering Code MRL ATSAM4S16CA-AU A ATSAM4S16BA-MU A 11100AS–ATARM–27-Oct-11 Flash (Kbytes) Package (Kbytes) 1024 QFP100 1024 QFN64 Temperature Package Type Operating Range Industrial Green -40°C to 105°C Industrial Green -40°C to 105°C 61 ...

  • Page 62

    Revision History In the table that follows, the most recent version of the document is referenced first. Doc. Rev Comments 11100AS Initial release 62 Change Request Ref. 11100AS–ATARM–27-Oct-11 ...

  • Page 63

    11100AS–ATARM–27-Oct-11 63 ...

  • Page 64

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