SAM4S16C

Manufacturer Part NumberSAM4S16C
ManufacturerAtmel Corporation
SAM4S16C datasheets
 


Specifications of SAM4S16C

Flash (kbytes)1024 KbytesPin Count100
# Of Touch Channels32Hardware Qtouch AcquisitionNo
Max I/o Pins79Ext Interrupts79
Usb Transceiver1Quadrature Decoder Channels2
Usb SpeedFull SpeedUsb InterfaceDevice
Spi3Twi (i2c)2
Uart4Ssc1
Sd / Emmc1Graphic LcdNo
Video DecoderNoCamera InterfaceNo
Adc Channels16Adc Resolution (bits)12
Adc Speed (ksps)1000Analog Comparators1
Resistive Touch ScreenNoDac Channels2
Dac Resolution (bits)12Temp. SensorYes
Crypto EngineNoSram (kbytes)128
Self Program MemoryYESExternal Bus Interface1
Dram MemoryNoNand InterfaceYes
PicopowerNoTemp. Range (deg C)-40 to 85
I/o Supply Class1.8/3.3Operating Voltage (vcc)1.62 to 3.6
FpuNoMpu / MmuYes / No
Timers6Output Compare Channels6
Input Capture Channels6Pwm Channels4
32khz RtcYesCalibrated Rc OscillatorYes
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Features
Core
®
®
– ARM
Cortex
-M4 running at up to 120 MHz
– Memory Protection Unit (MPU)
– DSP Instruction Set
®
– Thumb
-2 instruction set
Pin-to-pin compatible with SAM3N, SAM3S products (48-, 64- and 100- pin versions)
and SAM7S legacy products (64-pin version)
Memories
– Up to 1024 Kbytes embedded Flash
– Up to 128 Kbytes embedded SRAM
– 16 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP routines
– 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash
support
System
– Embedded voltage regulator for single supply operation
– Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation
– Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure
Detection and optional low-power 32.768 kHz for RTC or device clock
– RTC with Gregorian and Persian Calendar mode, waveform generation in low-
power modes
– RTC clock calibration circuitry for 32.768 kHz crystal frequency compensation
– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default
frequency for device startup. In-application trimming access for frequency
adjustment
– Slow Clock Internal RC oscillator as permanent low-power mode device clock
– Two PLLs up to 240 MHz for device clock and for USB
– Temperature Sensor
– Up to 24 Peripheral DMA (PDC) Channels
Low Power Modes
– Sleep and Backup modes, down to 3 µA in Backup mode
– Ultra low-power RTC
Peripherals
– USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints. On-Chip
Transceiver
– Up to 2 USARTs with ISO7816, IrDA
– Two 2-wire UARTs
– Up to 2 Two Wire Interface (I2C compatible), 1 SPI, 1 Serial Synchronous Controller
(I2S), 1 High Speed Multimedia Card Interface (SDIO/SD Card/MMC)
– 2 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and PWM
mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper
Motor
– 4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time
Generator Counter for Motor Control
– 32-bit Real-time Timer and RTC with calendar and alarm features
– Up to 16-channel, 1Msps ADC with differential input mode and programmable gain
stage and auto calibration
– One 2-channel 12-bit 1Msps DAC
– One Analog Comparator with flexible input selection, Selectable input hysteresis
– 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
I/O
– Up to 79 I/O lines with external interrupt capability (edge or level sensitivity),
debouncing, glitch filtering and on-die Series Resistor Termination
– Three 32-bit Parallel Input/Output Controllers, Peripheral DMA assisted Parallel
Capture Mode
Packages
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm
– 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-pad QFN 9x9 mm, pitch 0.5 mm
– 48-lead LQFP, 7 x 7 mm, pitch 0.5 mm/48-pad QFN 7x7 mm, pitch 0.5 mm
®
, RS-485, SPI, Manchester and Modem Mode
AT91SAM
ARM-based
Flash MCU
SAM4S Series
11100A–ATARM–28-Oct-11

SAM4S16C Summary of contents

  • Page 1

    Features • Core ® ® – ARM Cortex -M4 running 120 MHz – Memory Protection Unit (MPU) – DSP Instruction Set ® – Thumb -2 instruction set • Pin-to-pin compatible with SAM3N, SAM3S products (48-, 64- and ...

  • Page 2

    ... SAM7S legacy series (64-pin versions). 1.1 Configuration Summary The SAM4S series devices differ in memory size, package and features. the configurations of the device family. Table 1-1. Configuration Summary Device Flash SRAM 1024 128 SAM4S16C Kbytes Kbytes 1024 128 SAM4S16B Kbytes Kbytes 1024 128 SAM4S16A Kbytes ...

  • Page 3

    Block Diagram Figure 2-1. SAM4S Series 100-pin version Block Diagram System Controller TST PCK0-PCK2 PLLA PMC PLLB RC Osc 12/8/4 MHz XIN 3-20 MHz XOUT Osc SUPC XIN32 Osc 32 kHz XOUT32 RC 32 kHz ERASE 8 GPBREG VDDIO ...

  • Page 4

    Figure 2-2. SAM4S Series 64-pin version Block Diagram System Controller TST PCK0-PCK2 PLLA PLLB RC Osc 12/8/4 MHz XIN 3-20 MHz XOUT Osc SUPC XIN32 Osc 32 kHz XOUT32 RC 32 kHz ERASE 8 GPBREG VDDIO VDDCORE RTT VDDPLL POR ...

  • Page 5

    Figure 2-3. SAM4S Series 48-pin version Block Diagram System Controller TST PCK0-PCK2 PLLA PLLB RC Osc 12/8/4 MHz XIN 3-20 MHz XOUT SUPC XIN32 Osc 32 kHz XOUT32 RC 32 kHz ERASE 8 GPBREG VDDIO VDDCORE VDDPLL RTCOUT0 RTCOUT1 RSTC ...

  • Page 6

    Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function Peripherals I/O Lines and USB transceiver VDDIO Power Supply Voltage Regulator Input, ADC, DAC and VDDIN Analog Comparator Power Supply VDDOUT Voltage Regulator Output VDDPLL Oscillator and ...

  • Page 7

    Table 3-1. Signal Description List (Continued) Signal Name Function Flash and NVM Configuration Bits Erase ERASE Command NRST Synchronous Microcontroller Reset TST Test Select URXDx UART Receive Data UTXDx UART Transmit Data PA0 - PA31 Parallel IO Controller A PB0 ...

  • Page 8

    Table 3-1. Signal Description List (Continued) Signal Name Function Universal Synchronous Asynchronous Receiver Transmitter USARTx SCKx USARTx Serial Clock TXDx USARTx Transmit Data RXDx USARTx Receive Data RTSx USARTx Request To Send CTSx USARTx Clear To Send DTR1 USART1 Data ...

  • Page 9

    Table 3-1. Signal Description List (Continued) Signal Name Function TWDx TWIx Two-wire Serial Data TWCKx TWIx Two-wire Serial Clock ADC, DAC and Analog Comparator ADVREF Reference AD0-AD14 Analog Inputs ADTRG ADC Trigger DAC0 - DAC1 Analog output DACTRG DAC Trigger ...

  • Page 10

    Package and Pinout SAM4S devices are pin-to-pin compatible with SAM3N, SAM3S products in 48-, 64- and 100-pin versions, and AT91SAM7S legacy products in 64-pin versions. 4.1 SAM4S16/S8C Package and Pinout 4.1.1 100-Lead LQFP Package Outline Figure 4-1. 4.1.2 100-ball ...

  • Page 11

    LQFP Pinout Table 4-1. SAM4S16/S8C 100-lead LQFP pinout 1 ADVREF 2 GND 3 PB0/AD4 4 PC29/AD13 5 PB1/AD5 6 PC30/AD14 7 PB2/AD6 8 PC31 9 PB3/AD7 10 VDDIN 11 VDDOUT PA17/PGMD5/ 12 AD0 13 PC26 PA18/PGMD6/ 14 AD1 ...

  • Page 12

    TFBGA Pinout Table 4-2. SAM4S16/S8C 100-ball TFBGA pinout A1 PB1/AD5 C6 A2 PC29 C7 A3 VDDIO C8 A4 PB9/PGMCK/XIN C9 A5 PB8/XOUT C10 A6 PB13/DAC0 D1 A7 DDP/PB11 D2 A8 DDM/PB10 D3 A9 TMS/SWDIO/PB6 D4 A10 JTAGSEL D5 ...

  • Page 13

    SAM4S16/S8B Package and Pinout 4.2.1 64-Lead LQFP Package Outline Figure 4-3. 4.2.2 64-lead QFN Package Outline Figure 4-4. 11100A–ATARM–28-Oct-11 Orientation of the 64-lead LQFP Package Orientation of the 64-lead QFN Package ...

  • Page 14

    LQFP and QFN Pinout Table 4-3. 64-pin SAM4S16/S8B pinout 1 ADVREF 17 2 GND 18 3 PB0/AD4 19 4 PB1/AD5 20 5 PB2/AD6 21 6 PB3/AD7 22 7 VDDIN 23 8 VDDOUT 24 PA17/PGMD5 AD0 PA18/PGMD6/ ...

  • Page 15

    SAM4S16/S8A Package and Pinout 4.3.1 48-Lead LQFP Package Outline Figure 4-5. 4.3.2 48-lead QFN Package Outline Figure 4-6. 11100A–ATARM–28-Oct-11 Orientation of the 48-lead LQFP Package Orientation of the 48-lead QFN Package ...

  • Page 16

    LQFP and QFN Pinout Table 4-4. 48-pin SAM4S16/S8A pinout 1 ADVREF 13 2 GND 14 3 PB0/AD4 15 4 PB1/AD5 16 5 PB2/AD6 17 6 PB3/AD7 18 7 VDDIN 19 8 VDDOUT 20 PA17/PGMD5 AD0 PA18/PGMD6/ ...

  • Page 17

    Power Considerations 5.1 Power Supplies The SAM4S has several types of power supply pins: • VDDCORE pins: Power the core, the embedded memories and the peripherals. Voltage ranges from 1.08V to 1.32V. • VDDIO pins: Power the Peripherals I/O ...

  • Page 18

    Figure 5-1. Note: Figure 5-2. Note: Figure 5-3 Since the PIO state is preserved when in backup mode, any free PIO line can be used to switch off the external regulator by driving the PIO line at low level (PIO ...

  • Page 19

    Figure 5-3. 5.4 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The power management controller can be used to adapt the frequency ...

  • Page 20

    Supply Monitor alarm • RTC alarm • RTT alarm 5.5.2 Wait Mode The purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a powered state for a startup time of ...

  • Page 21

    Low Power Mode Summary Table The modes detailed above are the main low-power modes. Each part can be set off sep- arately and wake up sources can be individually configured. of the configurations of the low-power ...

  • Page 22

    Wake-up Sources The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they ...

  • Page 23

    Fast Startup The SAM4S allows the processor to restart in a few microseconds while the processor is in wait mode or in sleep mode. A fast start up can occur upon detection of a low level on one of ...

  • Page 24

    Input/Output Lines The SAM4S has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be ...

  • Page 25

    Table 6-1. System I/O Configuration Pin List. SYSTEM_IO Default function bit number after reset 12 ERASE 10 DDM 11 DDP 7 TCK/SWCLK 6 TMS/SWDIO 5 TDO/TRACESWO 4 TDI - PA7 - PA8 - PB9 - PB8 Notes PB12 ...

  • Page 26

    Test Pin The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM4S series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it ...

  • Page 27

    Product Mapping Figure 7-1. SAM4S Product Mapping Code 0x00000000 Boot Memory 0x00400000 Internal Flash 0x00800000 Internal ROM 0x00C00000 Reserved 0x1FFFFFFF External RAM 0x60000000 SMC Chip Select 0 0x61000000 SMC Chip Select 1 0x62000000 SMC Chip Select 2 0x63000000 SMC ...

  • Page 28

    Memories 8.1 Embedded Memories 8.1.1 Internal SRAM The SAM4S16 device (1024 Kbytes) embeds a total of 128-Kbytes high-speed SRAM. The SAM4S8 device (512 Kbytes) embeds a total of 128-Kbytes high-speed SRAM. The SRAM is accessible over System Cortex-M4 bus ...

  • Page 29

    For sector 0: • The smaller sector 0 has 16 pages of 512Bytes • The smaller sector 1 has 16 pages of 512 Bytes • The larger sector has 96 pages of 512 Bytes From Sector The ...

  • Page 30

    Refer to Figure 8-3. Erasing the memory can be performed as follows: • 512-byte page inside a sector Bytes • 4-Kbyte Block inside a sector of 8 KBytes/48 Kbytes/64 KBytes • sector ...

  • Page 31

    Lock Regions Several lock bits are used to protect write and erase operations on lock regions. A lock region is composed of several consecutive pages, and each lock region has its associated lock bit. Table 8- locked-region’s ...

  • Page 32

    The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. 8.1.3.10 SAM-BA Boot The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the on-chip Flash memory. The SAM-BA ...

  • Page 33

    Programmable Data Float Time per Chip Select • External Wait Request • Automatic Switch to Slow Clock Mode • Asynchronous Read in Page Mode Supported: Page Size Ranges from Bytes • NAND Flash additional logic supporting ...

  • Page 34

    Figure 9-1. System Controller Block Diagram VDDIO Zero-Power Power-on Reset Supply Monitor (Backup) WKUP0 - WKUP15 General Purpose Backup Registers SLCK SLCK XIN32 Xtal 32 kHz Oscillator XOUT32 Embedded 32 kHz RC Oscillator Backup Power Supply NRST FSTT0 - FSTT15 ...

  • Page 35

    System Controller and Peripheral Mapping Refer to All the peripherals are in the bit band region and are mapped in the bit band alias region. 9.2 Power-on-Reset, Brownout and Supply Monitor The SAM4S embeds three features to monitor, warn ...

  • Page 36

    Peripherals 10.1 Peripheral Identifiers Table 10-1 the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and control of the peripheral clock with the Power Management Controller. Table 10-1. Peripheral Identifiers Instance ID Instance Name 0 SUPC ...

  • Page 37

    Table 10-1. Peripheral Identifiers (Continued) Instance ID Instance Name 31 PWM 32 CRCCU 33 ACC 34 UDP 10.2 Peripheral Signal Multiplexing on I/O Lines The SAM4S features 2 PIO controllers on 48-pin, 64-pin versions (PIOA and PIOB PIO ...

  • Page 38

    PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A (PIOA) I/O Line Peripheral A Peripheral B PA0 PWMH0 TIOA0 PA1 PWMH1 TIOB0 PA2 PWMH2 SCK0 PA3 TWD0 NPCS3 PA4 TWCK0 TCLK0 PA5 RXD0 NPCS3 PA6 TXD0 PCK0 ...

  • Page 39

    PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B (PIOB) I/O Line Peripheral A Peripheral B PB0 PWMH0 PB1 PWMH1 PB2 URXD1 NPCS2 PB3 UTXD1 PCK2 PB4 TWD1 PWMH2 PB5 TWCK1 PWML0 PB6 PB7 PB8 PB9 PB10 ...

  • Page 40

    PIO Controller C Multiplexing Table 10-4. Multiplexing on PIO Controller C (PIOC) I/O Line Peripheral A PC0 D0 PC1 D1 PC2 D2 PC3 D3 PC4 D4 PC5 D5 PC6 D6 PC7 D7 PC8 NWE PC9 NANDOE PC10 NANDWE PC11 ...

  • Page 41

    ARM Cortex-M4 11.1 Description The Cortex-M4 processor is a high performance 32-bit processor designed for the microcon- troller market. It offers significant benefits to developers, including outstanding processing performance combined with fast interrupt handling, enhanced system debug with extensive ...

  • Page 42

    Integrated Configurable Debug The Cortex-M4 processor implements a complete hardware debug solution. This provides high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal ...

  • Page 43

    Block Diagram Figure 11-1. TTypical Cortex-M4 Implementation 11100A–ATARM–28-Oct-11 11100A–ATARM–28-Oct-11 Cortex-M4 Processor NVIC Processor Core Debug Memory Access Protection Unit Port Flash Data Patch Watchpoints Bus Matrix Code Interface Peripheral Interface SAM4S SAM4S Serial Wire Viewer SRAM and 43 43 ...

  • Page 44

    Cortex-M4 Models 11.4.1 Programmers Model This section describes the Cortex-M4 programmers model. In addition to the individual core reg- ister descriptions, it contains information about the processor modes and privilege levels for software execution and stacks. 11.4.1.1 Processor Modes ...

  • Page 45

    The options for processor operations are: Table 11-1. Processor Mode Thread Handler Note: 11.4.1.3 Core Registers Figure 11-2. Processor Core Registers Low registers High registers Stack Pointer Link Register Program Counter Table 11-2. Core Processor Registers Register General-purpose registers Stack ...

  • Page 46

    Table 11-2. Core Processor Registers Register Link Register Program Counter Program Status Register Application Program Status Register Interrupt Program Status Register Execution Program Status Register Priority Mask Register Fault Mask Register Base Priority Mask Register CONTROL register Notes: 1. Describes ...

  • Page 47

    Program Status Register Name: PSR Access: Read-write Reset: 0x000000000 The Program Status Register (PSR) combines: • Application Program Status Register (APSR) • Interrupt Program Status Register (IPSR) • Execution ...

  • Page 48

    Application Program Status Register Name: APSR Access: Read-write Reset: 0x000000000 – The APSR contains the current state of the condition flags from previous instruction executions. • N: Negative Flag ...

  • Page 49

    Interrupt Program Status Register Name: IPSR Access: Read-write Reset: 0x000000000 The IPSR contains the exception type number of the current Interrupt Service Routine (ISR). • ISR_NUMBER: Number of the Current Exception ...

  • Page 50

    Execution Program Status Register Name: EPSR Access: Read-write Reset: 0 0x00000000 The EPSR contains the Thumb state bit, and the execution state bits for either the If-Then (IT) instruction, or the ...

  • Page 51

    Exception Mask Registers The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they might impact on timing critical tasks. To access the exception mask registers use the MSR and MRS instructions, or the ...

  • Page 52

    Fault Mask Register Name: FAULTMASK Access: Read-write Reset: 0 0x00000000 The FAULTMASK register prevents the activation of all exceptions except for Non-Maskable Interrupt (NMI). • FAULTMASK 0: No effect. 1: Prevents ...

  • Page 53

    Base Priority Mask Register Name: BASEPRI Access: Read-write Reset: 0 0x00000000 The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents ...

  • Page 54

    CONTROL Register Name: CONTROL Access: Read-write Reset: 0 0x00000000 The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. • ...

  • Page 55

    Exceptions and Interrupts The Cortex-M4 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses the Handler ...

  • Page 56

    Memory Model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4GB of addressable memory. Figure 11-3. Memory Map 0x43FFFFFF 0x42000000 ...

  • Page 57

    Memory Types • Normal The processor can re-order transactions for efficiency, or perform speculative reads. • Device The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory. • Strongly-ordered The processor preserves transaction order relative to ...

  • Page 58

    Means that the memory system does not guarantee the ordering of the accesses. < Means that accesses are observed in program order, that is always observed before A2. 11.4.2.3 Behavior of Memory Accesses The behavior of accesses ...

  • Page 59

    Table 11-5. Address Range 0x60000000- 0x7FFFFFFF 0x80000000- 0x9FFFFFFF 0xA0000000- 0xBFFFFFFF 0xC0000000- 0xDFFFFFFF 0xE0000000- 0xE00FFFFF 0xE0100000- 0xFFFFFFFF Notes: Instruction Prefetch And Branch Prediction The Cortex-M4 processor: • prefetches instructions ahead of execution • speculatively prefetches from branch target addresses. 11.4.2.4 Software ...

  • Page 60

    MPU Programming Use a DSB followed by an ISB instruction or exception return to ensure that the new MPU con- figuration is used by subsequent instructions. 11.4.2.5 Bit-banding A bit-band region maps each word in a bit-band alias region to ...

  • Page 61

    Bit_band_base is the starting address of the alias region. • Byte_offset is the number of the byte in the bit-band region that contains the targeted bit. • Bit_number is the bit position, 0-7, of the targeted bit. Figure 11-4 ...

  • Page 62

    Directly Accessing a Bit-band Region “Behavior of Memory Accesses” accesses to the bit-band regions. 11.4.2.6 Memory Endianness The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first ...

  • Page 63

    To perform an exclusive read-modify-write of a memory location, the software must: 1. Use a Load-Exclusive instruction to read the value of the location. 2. Update the value, as required. 3. Use a Store-Exclusive instruction to attempt to write the ...

  • Page 64

    Table 11-8. Instruction STREX STREXH STREXB CLREX The actual exclusive access instruction generated depends on the data type of the pointer passed to the intrinsic function. For example, the following C code generates the require LDREXB operation: __ldrex((volatile char *) ...

  • Page 65

    Exception Model This section describes the exception model. 11.4.3.1 Exception States Each exception is in one of the following states: Inactive The exception is not active and not pending. Pending The exception is waiting to be serviced by the ...

  • Page 66

    Memory Management Fault (MemManage) A Memory Management Fault is an exception that occurs because of a memory protection related fault. The MPU or the fixed memory protection constraints determines this fault, for both instruction and data memory transactions. This fault ...

  • Page 67

    Table 11-9. Properties of the Different Exception Types (Continued) Exception (1) (1) Number Irq Number 4 -12 5 -11 6 -10 7- 12- and above 0 and above Notes ...

  • Page 68

    Vector Table The vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for all exception handlers. tion vectors in the vector table. The least-significant bit of each vector must be ...

  • Page 69

    Note: For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0]. If multiple pending ...

  • Page 70

    This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. Late-arriving This ...

  • Page 71

    Figure 11-6. Exception Stack Frame Exception frame with floating-point storage Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. The alignment of the stack frame is controlled via the STKALIGN bit of the Configuration Control ...

  • Page 72

    Exception Return An Exception return occurs when the processor is in Handler mode and executes one of the fol- lowing instructions to load the EXC_RETURN value into the PC: • an LDM • an LDR • EXC_RETURN is ...

  • Page 73

    Table 11-11. Faults (Continued) Fault MPU or default memory map mismatch: on instruction access on data access during exception stacking during exception unstacking during lazy floating-point state preservation Bus error: during exception stacking during exception unstacking during instruction prefetch during ...

  • Page 74

    A fault occurs and the handler for that fault is not enabled bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. This means ...

  • Page 75

    Power Management The Cortex-M4 processor sleep modes reduce the power consumption: • Sleep mode stops the processor clock • Deep sleep mode stops the system clock and switches off the PLL and flash memory. The SLEEPDEEP bit of the ...

  • Page 76

    Wakeup from WFE The processor wakes up if: • it detects an exception with sufficient priority to cause an exception entry • it detects an external event signal. See • multiprocessor system, another processor in the system ...

  • Page 77

    Cortex-M4 Instruction Set 11.6.1 Instruction Set Summary The processor implements a version of the Thumb instruction set. ported instructions. • angle brackets, <>, enclose alternative forms of the operand • braces, {}, enclose optional operands • the Operands column ...

  • Page 78

    Table 11-13. Cortex-M4 Instructions (Continued) Mnemonic Operands IT - LDM Rn{!}, reglist LDMDB, LDMEA Rn{!}, reglist LDMFD, LDMIA Rn{!}, reglist LDR Rt, [Rn, #offset] LDRB, LDRBT Rt, [Rn, #offset] LDRD Rt, Rt2, [Rn, #offset] LDREX Rt, [Rn, #offset] LDREXB Rt, ...

  • Page 79

    Table 11-13. Cortex-M4 Instructions (Continued) Mnemonic Operands QDSUB {Rd,} Rn, Rm QSAX {Rd,} Rn, Rm QSUB {Rd,} Rn, Rm QSUB16 {Rd,} Rn, Rm QSUB8 {Rd,} Rn, Rm RBIT Rd, Rn REV Rd, Rn REV16 Rd, Rn REVSH Rd, Rn ROR, ...

  • Page 80

    Table 11-13. Cortex-M4 Instructions (Continued) Mnemonic Operands SMULBB, SMULBT {Rd,} Rn, Rm SMULTB, SMULTT SMULL RdLo, RdHi, Rn, Rm SMULWB, SMULWT {Rd,} Rn, Rm SMUSD, SMUSDX {Rd,} Rn, Rm SSAT Rd, #n, Rm {,shift #s} SSAT16 Rd, #n, Rm SSAX ...

  • Page 81

    Table 11-13. Cortex-M4 Instructions (Continued) Mnemonic Operands UHSUB16 {Rd,} Rn, Rm UHSUB8 {Rd,} Rn, Rm UBFX Rd, Rn, #lsb, #width UDIV {Rd,} Rn, Rm UMAAL RdLo, RdHi, Rn, Rm UMLAL RdLo, RdHi, Rn, Rm UMULL RdLo, RdHi, Rn, Rm UQADD16 ...

  • Page 82

    Table 11-13. Cortex-M4 Instructions (Continued) Mnemonic Operands VLMA.F32 {Sd,} Sn, Sm VLMS.F32 {Sd,} Sn, Sm VMOV.F32 Sd, #imm VMOV Sd, Sm VMOV Sn, Rt VMOV Sm, Sm1, Rt, Rt2 VMOV Dd[x], Rt VMOV Rt, Dn[x] VMRS Rt, FPSCR VMSR FPSCR, ...

  • Page 83

    Table 11-14. CMSIS Functions to Generate some Cortex-M4 Instructions (Continued) Instruction REVSH RBIT SEV WFE WFI The CMSIS also provides a number of functions for accessing the special registers using MRS and MSR instructions: Table 11-15. CMSIS Intrinsic Functions to ...

  • Page 84

    Flexible Second Operand Many general data processing instructions have a flexible second operand. This is shown as Operand2 in the descriptions of the syntax of each instruction. Operand2 can be a: • “Constant” • “Register with Optional Shift” Constant ...

  • Page 85

    If the user omits the shift, or specifies LSL #0, the instruction uses the value in Rm. If the user specifies a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used by ...

  • Page 86

    When the instruction is LSRS or when LSR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the ...

  • Page 87

    32, then the value of the result is same as the value in Rm, and if the carry flag is updated updated to bit[31] of Rm. • ROR with shift length, n, more than ...

  • Page 88

    UNALIGN_TRP bit in the Configuration and Control Register to trap all unaligned accesses, see “Configuration and Control Register” 11.6.3.6 PC-relative Expressions A PC-relative expression or label is a symbol that represents the address of an instruction or lit- eral ...

  • Page 89

    The APSR contains the following condition flags For more information about the APSR, see A carry occurs: • if the result of an addition is greater than or equal to 2 • if the result of ...

  • Page 90

    Table 11-16. Condition Code Suffixes (Continued) Suffix Absolute Value The example below shows the use of a conditional instruction to find the absolute value of a number ABS(R1). Compare ...

  • Page 91

    Memory Access Instructions The table below shows the memory access instructions: Table 11-17. Memory Access Instructions Mnemonic ADR CLREX LDM{mode} LDR{type} LDR{type} LDR{type}T LDR LDRD LDREX{type} POP PUSH STM{mode} STR{type} STR{type} STR{type}T STREX{type} 11100A–ATARM–28-Oct-11 11100A–ATARM–28-Oct-11 Description Load PC-relative address ...

  • Page 92

    ADR Load PC-relative address. Syntax ADR{cond} Rd, label where: cond Rd label Operation ADR determines the address by adding an immediate value to the PC, and writes the result to the destination register. ADR produces position-independent code, because the ...

  • Page 93

    LDR and STR, Immediate Offset Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset. Syntax op{type}{cond} Rt, [Rn {, #offset}] op{type}{cond} Rt, [Rn, #offset]! op{type}{cond} Rt, [Rn], #offset opD{cond} Rt, Rt2, [Rn {, #offset}] opD{cond} ...

  • Page 94

    Post-indexed Addressing The address obtained from the register Rn is used as the address for the memory access. The offset value is added to or subtracted from the address, and written back into the register Rn. The assembly ...

  • Page 95

    LDR R8, [R10] LDRNE R2, [R5, #960]! STR R2, [R9,#const-struc] STRH R3, [R4], #4 LDRD R8, R9, [R3, #0x20] STRD R0, R1, [R8], #-16 11100A–ATARM–28-Oct-11 11100A–ATARM–28-Oct-11 ; Loads R8 from the address in R10. ; Loads (conditionally) R2 from a ...

  • Page 96

    LDR and STR, Register Offset Load and Store with register offset. Syntax op{type}{cond} Rt, [Rn LSL #n}] where: op LDR STR type cond LSL #n Operation LDR instructions load ...

  • Page 97

    These instructions do not change the flags. Examples STR R0, [R5, R1] LDRSB R0, [R5, R1, LSL #1] ; Read byte value from an address equal to STR R0, [R1, R2, LSL #2] ; Stores address equal ...

  • Page 98

    LDR and STR, unprivileged Load and Store with unprivileged access. Syntax op{type}T{cond} Rt, [Rn {, #offset}] where: op LDR STR type is one of cond Rt Rn offset Operation These load and store instructions ...

  • Page 99

    LDR, PC-relative Load register from memory. Syntax LDR{type}{cond} Rt, label LDRD{cond} Rt, Rt2, label where: type cond Rt Rt2 label Operation LDR loads a register with a value from a PC-relative memory address. The ...

  • Page 100

    IT block. Condition Flags These instructions do not change the flags. Examples LDR R0, LookUpTable LDRSB R7, localdata SAM4S SAM4S 100 100 ; Load R0 with ...

  • Page 101

    LDM and STM Load and Store Multiple registers. Syntax op{addr_mode}{cond} Rn{!}, reglist where: op LDM STM addr_mode IA DB cond Rn ! into Rn. reglist LDM and LDMFD are synonyms for LDMIA. LDMFD refers to its use for popping ...

  • Page 102

    The accesses happen in order of decreasing register numbers, with the highest numbered regis- ter using the highest memory address and the lowest number register using the lowest memory address. If the writeback suffix is specified, the value of Rn ...

  • Page 103

    PUSH and POP Push registers onto, and pop registers off a full-descending stack. Syntax PUSH{cond} reglist POP{cond} reglist where: cond reglist PUSH and POP are synonyms for STMDB and LDM (or LDMIA) with the memory addresses for the access ...

  • Page 104

    LDREX and STREX Load and Store Register Exclusive. Syntax LDREX{cond} Rt, [Rn {, #offset}] STREX{cond} Rd, Rt, [Rn {, #offset}] LDREXB{cond} Rt, [Rn] STREXB{cond} Rd, Rt, [Rn] LDREXH{cond} Rt, [Rn] STREXH{cond} Rd, Rt, [Rn] where: cond ...

  • Page 105

    Condition Flags These instructions do not change the flags. Examples try 11.6.4.9 CLREX Clear Exclusive. Syntax CLREX{cond} where: cond Operation Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination register and fail to ...

  • Page 106

    General Data Processing Instructions The table below shows the data processing instructions: Table 11-20. Data Processing Instructions Mnemonic ADC ADD ADDW AND ASR BIC CLZ CMN CMP EOR LSL LSR MOV MOVT MOVW MVN ORN ORR RBIT REV REV16 ...

  • Page 107

    Table 11-20. Data Processing Instructions (Continued) Mnemonic SHSUB16 SHSUB8 SSUB16 SSUB8 SUB SUBW TEQ TST UADD16 UADD8 UASX USAX UHADD16 UHADD8 UHASX UHSAX UHSUB16 UHSUB8 USAD8 USADA8 USUB16 USUB8 11100A–ATARM–28-Oct-11 11100A–ATARM–28-Oct-11 Description Signed Halving Subtract 16 Signed Halving Subtract 8 ...

  • Page 108

    ADD, ADC, SUB, SBC, and RSB Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract. Syntax op{S}{cond} {Rd,} Rn, Operand2 op{cond} {Rd,} Rn, #imm12 where cond Rd Rn Operand2 imm12 Operation The ADD The ADC ...

  • Page 109

    IT block • with the exception of the only with the additional restrictions: – the user must not specify the S suffix – the second operand ...

  • Page 110

    AND, ORR, EOR, BIC, and ORN Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT. Syntax op{S}{cond} {Rd,} Rn, Operand2 where cond Rd Rn Operand2 Operation The AND the values in The BIC responding bits in ...

  • Page 111

    ASR, LSL, LSR, ROR, and RRX Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend. Syntax op{S}{cond} Rd, Rm, Rs op{S}{cond} Rd, Rm, #n RRX{S}{cond} Rd, Rm where ...

  • Page 112

    ASR LSLS R1, R2 Logical shift left by 3 bits with flag update LSR ROR RRX SAM4S SAM4S 112 112 R7, R8 Arithmetic shift right by 9 bits R4, R5 Logical shift right by ...

  • Page 113

    CLZ Count Leading Zeros. Syntax CLZ{cond} Rd, Rm where: cond Rd Rm Operation The CLZ . The result value bits are set and zero if bit[31] is set. Rd Restrictions Do not use SP and ...

  • Page 114

    CMP and CMN Compare and Compare Negative. Syntax CMP{cond} Rn, Operand2 CMN{cond} Rn, Operand2 where: cond Rn Operand2 Operation These instructions compare the value in a register with on the result, but do not write the result to a ...

  • Page 115

    MOV and MVN Move and Move NOT. Syntax MOV{S}{cond} Rd, Operand2 MOV{cond} Rd, #imm16 MVN{S}{cond} Rd, Operand2 where: S cond Rd Operand2 imm16 Operation The MOV When Operand2 is the corresponding shift instruction: • ASR{S}{cond} Rd, Rm, #n • ...

  • Page 116

    Though it is possible to use or BX BLX Condition Flags If is specified, these instructions: S • update the N and Z flags ...

  • Page 117

    MOVT Move Top. Syntax MOVT{cond} Rd, #imm16 where: cond Rd imm16 Operation writes a 16-bit immediate value, MOVT ister. The write does not affect The MOV Restrictions must not be SP and must not be PC. Rd Condition Flags ...

  • Page 118

    REV, REV16, REVSH, and RBIT Reverse bytes and Reverse bits. Syntax op{cond} Rd, Rn where: op cond Rd Rn Operation Use these instructions to change endianness of data: converts either: REV • 32-bit big-endian data into little-endian data • ...

  • Page 119

    SADD16 and SADD8 Signed Add 16 and Signed Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op cond Operation Use these instructions to perform a halfword or byte add in parallel: The SADD16 1. Adds each halfword ...

  • Page 120

    SHADD16 and SHADD8 Signed Halving Add 16 and Signed Halving Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op cond Operation Use these instructions to add 16-bit and 8-bit data and then to halve the result before ...

  • Page 121

    SHASX and SHSAX Signed Halving Add and Subtract with Exchange and Signed Halving Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm where: op cond Rd Rn, Rm Operation The SHASX 1. Adds the top halfword of the ...

  • Page 122

    SHSUB16 and SHSUB8 Signed Halving Subtract 16 and Signed Halving Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: op cond Operation Use these instructions to add 16-bit and 8-bit data and then to halve the result before ...

  • Page 123

    SSUB16 and SSUB8 Signed Subtract 16 and Signed Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: op cond Operation Use these instructions to change endianness of data: The SSUB16 1. Subtracts each halfword from the second operand ...

  • Page 124

    SASX and SSAX Signed Add and Subtract with Exchange and Signed Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rm, Rn where: op cond Rd Rn, Rm Operation The SASX 1. Adds the signed top halfword of the first ...

  • Page 125

    TST and TEQ Test bits and Test Equivalence. Syntax TST{cond} Rn, Operand2 TEQ{cond} Rn, Operand2 where: cond Rn Operand2 Operation These instructions test the value in a register against based on the result, but do not write the result ...

  • Page 126

    Operation Use these instructions to add 16- and 8-bit unsigned data: The UADD16 1. adds each halfword from the first operand to the corresponding halfword of the second operand. 2. writes the unsigned result ...

  • Page 127

    UASX and USAX Add and Subtract with Exchange and Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm where: op cond Rd Rn, Rm Operation The UASX 1. Subtracts the top halfword of the second operand from the ...

  • Page 128

    UHADD16 and UHADD8 Unsigned Halving Add 16 and Unsigned Halving Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op cond Operation Use these instructions to add 16- and 8-bit data and then to halve the result before ...

  • Page 129

    UHASX and UHSAX Unsigned Halving Add and Subtract with Exchange and Unsigned Halving Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm where: op cond Rd Rn, Rm Operation The UHASX 1. Adds the top halfword of the ...

  • Page 130

    UHSAX SAM4S SAM4S 130 130 ; Subtracts top halfword of R2 from bottom halfword and writes halved result to bottom halfword of R7 R0, R3 Subtracts bottom halfword of R5 from top halfword of ; ...

  • Page 131

    UHSUB16 and UHSUB8 Unsigned Halving Subtract 16 and Unsigned Halving Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: op cond Operation Use these instructions to add 16-bit and 8-bit data and then to halve the result before ...

  • Page 132

    SEL Select Bytes. Selects each byte of its result from either its first operand or its second operand, according to the values of the GE flags. Syntax SEL{<c>}{<q>} {<Rd>,} <Rn>, <Rm> where: <c>, <q> <Rd> <Rn> <Rm> Operation The ...

  • Page 133

    USAD8 Unsigned Sum of Absolute Differences Syntax USAD8{cond}{Rd,} Rn, Rm where: cond Operation The USAD8 1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register. 2. Adds the ...

  • Page 134

    USADA8 Unsigned Sum of Absolute Differences and Accumulate Syntax USADA8{cond}{Rd,} Rn, Rm, Ra where: cond Operation The USADA8 1. Subtracts each byte of the second operand register from the corresponding byte of the first operand ...

  • Page 135

    USUB16 and USUB8 Unsigned Subtract 16 and Unsigned Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: op cond Operation Use these instructions to subtract 16-bit and 8-bit data before writing the result to the destination register: The ...

  • Page 136

    Multiply and Divide Instructions The table below shows the multiply and divide instructions: Table 11-21. Multiply and Divide Instructions Mnemonic MLA MLS MUL SDIV SMLA[B,T] SMLAD, SMLADX SMLAL SMLAL[B,T] SMLALD, SMLALDX SMLAW[B|T] SMLSD SMLSLD SMMLA SMMLS, SMMLSR SMUAD, SMUADX ...

  • Page 137

    MUL, MLA, and MLS Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and pro- ducing a 32-bit result. Syntax MUL{S}{cond} {Rd,} Rn Multiply MLA{cond} Rd, Rn, Rm Multiply with accumulate MLS{cond} Rd, ...

  • Page 138

    UMULL, UMAAL, UMLAL Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result. Syntax op{cond} RdLo, RdHi, Rn, Rm where: op cond RdHi, RdLo Rn, Rm Operation These instructions interpret the values from The UMULL ...

  • Page 139

    SMLA and SMLAW Signed Multiply Accumulate (halfwords). Syntax op{XY}{cond} Rd, Rn, Rm op{Y}{cond} Rd, Rn, Rm, Ra where op cond Rd Rn Operation The SMALBB • Multiplies the specified signed halfword, top or bottom, values from • ...

  • Page 140

    Examples SMLABB R5, R6, R4, R1 SMLATB R5, R6, R4, R1 SMLATT R5, R6, R4, R1 SMLABT R5, R6, R4, R1 SMLABT R4, R3, R2 SMLAWB R10, R2, R5 Multiplies R2 with bottom halfword of R5, adds SMLAWT ...

  • Page 141

    SMLAD Signed Multiply Accumulate Long Dual Syntax op{X}{cond} Rd, Rn, Rm where: op cond Operation The SMLAD and SMLAD • not present, multiply the top signed halfword value in X and ...

  • Page 142

    RdLo, RdHi, Rn, Rm op{XY}{cond} RdLo, RdHi, Rn, Rm op{X}{cond} RdLo, RdHi, Rn, Rm where: op cond RdHi, RdLo Rn, Rm Operation The SMLAL • Multiplies the two’s complement signed word values from • Adds the 64-bit value in ...

  • Page 143

    In these instructions: • do not use SP and do not use PC. • RdHi Condition Flags These instructions do not affect the condition code flags. Examples SMLAL SMLALBT SMLALTB SMLALD SMLALDX 11100A–ATARM–28-Oct-11 11100A–ATARM–28-Oct-11 and must be different registers. RdLo ...

  • Page 144

    SMLSD and SMLSLD Signed Multiply Subtract Dual and Signed Multiply Subtract Long Dual Syntax op{X}{cond} Rd, Rn, Rm, Ra where: op cond Rd Rn Operation The SMLSD halfwords. This instruction: • Optionally rotates the halfwords of the ...

  • Page 145

    SMLSD SMLSDX SMLSLD SMLSLDX 11100A–ATARM–28-Oct-11 11100A–ATARM–28-Oct-11 R0, R4, R5 Multiplies bottom halfword of R4 with bottom ; halfword of R5, multiplies top halfword with top halfword of R5, subtracts second from ; first, adds R6, ...

  • Page 146

    SMMLA and SMMLS Signed Most Significant Word Multiply Accumulate and Signed Most Significant Word Multiply Subtract Syntax op{R}{cond} Rd, Rn, Rm, Ra where cond Rd Rn Operation The SMMLA The SMMLA • Multiplies the values ...

  • Page 147

    SMMLAR SMMLSR SMMLS 11.6.6.8 SMMUL Signed Most Significant Word Multiply Syntax op{R}{cond} Rd, Rn, Rm where cond Rd Rn, Rm Operation The SMMUL integers. The • Multiplies the values from • Optionally rounds the result, otherwise truncates the ...

  • Page 148

    SMUAD and SMUSD Signed Dual Multiply Add and Signed Dual Multiply Subtract Syntax op{X}{cond} Rd, Rn, Rm where: op cond Rd Rn, Rm Operation The SMUAD halfwords in each operand. This instruction: • Optionally rotates the halfwords of the ...

  • Page 149

    SMUSD SMUSDX R4, R5, R3 11100A–ATARM–28-Oct-11 11100A–ATARM–28-Oct- R4, adds multiplication of top halfword with bottom halfword of R4, writes to R3 R3, R6 Multiplies bottom halfword of R4 with bottom halfword ; of ...

  • Page 150

    SMUL and SMULW Signed Multiply (halfwords) and Signed Multiply (word by halfword) Syntax op{XY}{cond} Rd,Rn, Rm op{Y}{cond} Rd. Rn, Rm For SMULXY op cond Rd Rn, Rm Operation The SMULBB signed 16-bit integers. These instructions: • Multiplies the specified ...

  • Page 151

    SMULTT SMULTB SMULWT SMULWB 11100A–ATARM–28-Oct-11 11100A–ATARM–28-Oct-11 ; writes to R0 R0, R4 Multiplies the top halfword of R4 with the top ; halfword of R5, multiplies results and writes ; to R0 R0, R4 Multiplies the ...

  • Page 152

    UMULL, UMLAL, SMULL, and SMLAL Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and pro- ducing a 64-bit result. Syntax op{cond} RdLo, RdHi, Rn, Rm where: op cond RdHi, RdLo Rn, Rm Operation The UMULL these ...

  • Page 153

    SDIV and UDIV Signed Divide and Unsigned Divide. Syntax SDIV{cond} {Rd,} Rn, Rm UDIV{cond} {Rd,} Rn, Rm where: cond Operation performs a signed integer division of the value in SDIV performs an unsigned integer division of ...

  • Page 154

    Saturating Instructions The table below shows the saturating instructions: Table 11-22. Saturating Instructions Mnemonic SSAT SSAT16 USAT USAT16 QADD QSUB QSUB16 QASX QSAX QDADD QDSUB UQADD16 UQADD8 UQASX UQSAX UQSUB16 UQSUB8 For signed n-bit saturation, this means that: • ...

  • Page 155

    SSAT and USAT Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating. Syntax op{cond} Rd, # shift #s} where: op cond Rd n ranges from for Rm shift ...

  • Page 156

    SSAT16 and USAT16 Signed Saturate and Unsigned Saturate to any bit position for two halfwords. Syntax op{cond} Rd, #n, Rm where: op cond Rd n ranges from for Rm Operation The SSAT16 Saturates two signed ...

  • Page 157

    QADD and QSUB Saturating Add and Saturating Subtract, signed. Syntax op{cond} {Rd}, Rn, Rm op{cond} {Rd}, Rn, Rm where: op cond Rd Rn, Rm Operation These instructions add or subtract two, four or eight values from the first and ...

  • Page 158

    QSUB16 R4, R2, R3 QSUB8 SAM4S SAM4S 158 158 ; R3 ; Subtracts halfwords of R3 from corresponding halfword ; of R2, saturates to 16 bits, writes to corresponding ; halfword of R4 R4, R2 Subtracts bytes of ...

  • Page 159

    QASX and QSAX Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, signed. Syntax op{cond} {Rd}, Rm, Rn where: op cond Rd Rn, Rm Operation The QASX 1. Adds the top halfword of the source ...

  • Page 160

    QSAX SAM4S SAM4S 160 160 R0, R3 Subtracts bottom halfword of R5 from top halfword of ; R3, saturates to 16 bits, writes to top halfword Adds bottom halfword top halfword of ...

  • Page 161

    QDADD and QDSUB Saturating Double and Add and Saturating Double and Subtract, signed. Syntax op{cond} {Rd}, Rm, Rn where: op cond Rd Rm, Rn Operation The QDADD • Doubles the second operand value. • Adds the result of the ...

  • Page 162

    UQASX and UQSAX Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, unsigned. Syntax op{cond} {Rd}, Rm, Rn where: type cond Rd Rn, Rm Operation The UQASX 1. Adds the bottom halfword of the source ...

  • Page 163

    R0 ; Adds bottom halfword top halfword saturates to 16 bits, writes to bottom halfword of R0. SAM4S SAM4S 163 163 ...

  • Page 164

    UQADD and UQSUB Saturating Add and Saturating Subtract Unsigned. Syntax op{cond} {Rd}, Rn, Rm op{cond} {Rd}, Rn, Rm where: op cond Rd Rn, Rm Operation These instructions add or subtract two or four values and then writes an unsigned ...

  • Page 165

    UQADD16 R7, R4 Adds halfwords corresponding halfword in R2, UQADD8 R4, R2 Adds bytes corresponding byte of R5, saturates UQSUB16 R6, R3 Subtracts halfwords in R0 from corresponding ...

  • Page 166

    Packing and Unpacking Instructions The table below shows the instructions that operate on packing and unpacking data: Table 11-23. Packing and Unpacking Instructions Mnemonic PKH SXTAB SXTAB16 SXTAH SXTB SXTB16 SXTH UXTAB UXTAB16 UXTAH UXTB UXTB16 UXTH SAM4S SAM4S ...

  • Page 167

    PKHBT and PKHTB Pack Halfword Syntax op{cond} {Rd}, Rn LSL #imm} op{cond} {Rd}, Rn ASR #imm} where: op cond imm Operation The PKHBT 1. Writes the value of the bottom halfword of ...

  • Page 168

    SXT and UXT Sign extend and Zero extend. Syntax op{cond} {Rd ROR #n} op{cond} {Rd ROR #n} where: op cond Rd Rm ROR #n Operation These instructions do the following: 1. Rotate the value from ...

  • Page 169

    SXTA and UXTA Signed and Unsigned Extend and Add Syntax op{cond} {Rd,} Rn ROR #n} op{cond} {Rd,} Rn ROR #n} where: op cond ROR #n Operation These instructions do the following: 1. ...

  • Page 170

    SXTAH R4, R8, R6, ROR #16 ; Rotates R6 right by 16 bits, obtains bottom UXTAB R3, R4, R10 SAM4S SAM4S 170 170 ; halfword, sign extends to 32 bits, adds R8,and ; writes Extracts bottom byte ...

  • Page 171

    Bitfield Instructions The table below shows the instructions that operate on adjacent sets of bits in registers or bitfields: Table 11-24. Packing and Unpacking Instructions Mnemonic BFC BFI SBFX SXTB SXTH UBFX UXTB UXTH 11100A–ATARM–28-Oct-11 11100A–ATARM–28-Oct-11 Description Bit Field ...

  • Page 172

    BFC and BFI Bit Field Clear and Bit Field Insert. Syntax BFC{cond} Rd, #lsb, #width BFI{cond} Rd, Rn, #lsb, #width where: cond Rd Rn lsb width Operation clears a bitfield in a register. It clears BFC bits in Rd ...

  • Page 173

    SBFX and UBFX Signed Bit Field Extract and Unsigned Bit Field Extract. Syntax SBFX{cond} Rd, Rn, #lsb, #width UBFX{cond} Rd, Rn, #lsb, #width where: cond Rd Rn lsb width Operation extracts a bitfield from one register, sign extends it ...

  • Page 174

    SXT and UXT Sign extend and Zero extend. Syntax SXTextend{cond} {Rd ROR #n} UXTextend{cond} {Rd ROR #n} where: extend cond Rd Rm ROR #n . Operation These instructions do the following: 1. Rotate the value ...

  • Page 175

    Branch and Control Instructions The table below shows the branch and control instructions: Table 11-25. Branch and Control Instructions Mnemonic B BL BLX BX CBNZ CBZ IT TBB TBH 11100A–ATARM–28-Oct-11 11100A–ATARM–28-Oct-11 Description Branch Branch with Link Branch indirect with ...

  • Page 176

    B, BL, BX, and BLX Branch instructions. Syntax B{cond} label BL{cond} label BX{cond} Rm BLX{cond} Rm where BLX cond label Rm Operation All these instructions cause a branch to • The R14). • The Bcond label ...

  • Page 177

    BX address created by changing bit[ • when any of these instructions is inside an IT block, it must be the last instruction of the IT block. is the only conditional instruction that is not required ...

  • Page 178

    CBZ and CBNZ Compare and Branch on Zero, Compare and Branch on Non-Zero. Syntax CBZ Rn, label CBNZ Rn, label where: Rn label Operation Use the number of instructions. CBZ Rn, label CMP BEQ CBNZ Rn, label CMP BNE ...

  • Page 179

    IT If-Then condition instruction. Syntax IT{x{y{z}}} cond where cond The condition switch for the second, third and fourth instruction in the IT block can be either possible to use instructions in the ...

  • Page 180

    ADD PC, PC, Rm – MOV PC, Rm – – any – • do not branch to any instruction inside an IT block, except when returning from an exception handler • all conditional instructions except or inside an IT ...

  • Page 181

    TBB and TBH Table Branch Byte and Table Branch Halfword. Syntax TBB [Rn, Rm] TBH [Rn, Rm, LSL #1] where Operation These instructions cause a PC-relative forward branch using a table of single byte offsets for , ...

  • Page 182

    BranchTable_H DCI DCI DCI CaseA ; an instruction sequence follows CaseB ; an instruction sequence follows CaseC ; an instruction sequence follows SAM4S SAM4S 182 182 ((CaseA - BranchTable_H)/2) ; CaseA offset calculation ((CaseB - BranchTable_H)/2) ; CaseB offset calculation ...

  • Page 183

    Miscellaneous Instructions The table below shows the remaining Cortex-M4 instructions: Table 11-27. Miscellaneous Instructions Mnemonic BKPT CPSID CPSIE DMB DSB ISB MRS MSR NOP SEV SVC WFE WFI 11100A–ATARM–28-Oct-11 11100A–ATARM–28-Oct-11 Description Breakpoint Change Processor State, Disable Interrupts Change Processor ...

  • Page 184

    BKPT Breakpoint. Syntax BKPT #imm where: imm Operation The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. imm is ignored ...

  • Page 185

    CPS Change Processor State. Syntax CPSeffect iflags where: effect IE ID iflags i f Operation CPS changes the PRIMASK and FAULTMASK special register values. See for more information about these registers. isters” Restrictions The restrictions are: • use CPS ...

  • Page 186

    DMB Data Memory Barrier. Syntax DMB{cond} where: cond Operation DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the DMB instruction are completed before any explicit memory accesses ...

  • Page 187

    DSB Data Synchronization Barrier. Syntax DSB{cond} where: cond Operation DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do not execute until the DSB instruction completes. The DSB instruction completes ...

  • Page 188

    ISB Instruction Synchronization Barrier. Syntax ISB{cond} where: cond Operation ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from memory again, after the ISB instruction ...

  • Page 189

    MRS Move the contents of a special register to a general-purpose register. Syntax MRS{cond} Rd, spec_reg where: cond Rd spec_reg Operation Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR, for example ...

  • Page 190

    MSR Move the contents of a general-purpose register into the specified special register. Syntax MSR{cond} spec_reg, Rn where: cond Rn spec_reg Operation The register access operation in MSR depends on the privilege level. Unprivileged software can only access the ...

  • Page 191

    NOP No Operation. Syntax NOP{cond} where: cond Operation NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the pipeline before it reaches the execution stage. Use NOP for padding, for example to ...

  • Page 192

    SEV Send Event. Syntax SEV{cond} where: cond Operation SEV is a hint instruction that causes an event to be signaled to all processors within a multipro- cessor system. It also sets the local event register to 1, see Condition ...

  • Page 193

    SVC Supervisor Call. Syntax SVC{cond} #imm where: cond imm Operation The SVC instruction causes the SVC exception. imm is ignored by the processor. If required, it can be retrieved by the exception handler to determine what service is being ...

  • Page 194

    WFE Wait For Event. Syntax WFE{cond} where: cond Operation WFE is a hint instruction. If the event register is 0, WFE suspends execution until one of the following events occurs: • an exception, unless masked by the exception mask ...

  • Page 195

    WFI Wait for Interrupt. Syntax WFI{cond} where: cond Operation WFI is a hint instruction that suspends execution until one of the following events occurs: • an exception • a Debug Entry request, regardless of whether Debug is enabled. Condition ...

  • Page 196

    Cortex-M4 Core Peripherals 11.7.1 Peripherals • Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC embedded interrupt controller that supports low latency interrupt processing. See Controller (NVIC)” • System Control Block (SCB) The System Control ...

  • Page 197

    Nested Vectored Interrupt Controller (NVIC) This section describes the NVIC and the registers it uses. The NVIC supports: • interrupts. • A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a ...

  • Page 198

    NVIC Design Hints and Tips Ensure that the software uses correctly aligned register accesses. The processor does not sup- port unaligned accesses to NVIC registers. See the individual register descriptions for the supported access sizes. A interrupt can enter ...

  • Page 199

    Interrupt Priority Registers map to an array of 4-bit integers, so that the array IP[0] to IP[34] corresponds to the registers IPR0-IPR8, and the array entry IP[n] holds the interrupt priority for interrupt n. ...

  • Page 200

    Nested Vectored Interrupt Controller (NVIC) User Interface Table 11-30. Nested Vectored Interrupt Controller (NVIC) Register Mapping Offset Register 0xE000E100 Interrupt Set-enable Register 0 ... ... 0xE000E11C Interrupt Set-enable Register 7 0XE000E180 Interrupt Clear-enable Register0 ... ... 0xE000E19C Interrupt Clear-enable ...