SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 1040

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
39.6.13
39.6.14
1040
1040
SAM4S
SAM4S
Fault Output
Write Protection Registers
ADC_SEQR2) the structure differs. Each data transferred to PDC buffer, carried on a half-word
(16-bit), consists of last converted data right aligned and when TAG is set in ADC_EMR register,
the 4 most significant bits are carrying the channel number thus allowing an easier post-process-
ing in the PDC buffer or better checking the PDC buffer integrity.
The ADC Controller internal fault output is directly connected to PWM fault input. Fault output
may be asserted according to the configuration of ADC_EMR (Extended Mode Register) and
ADC_CWR (Compare Window Register) and converted values. When the Compare occurs, the
ADC fault output generates a pulse of one Master Clock Cycle to the PWM fault input. This fault
line can be enabled or disabled within PWM. Should it be activated and asserted by the ADC
Controller, the PWM outputs are immediately placed in a safe state (pure combinational path).
Note that the ADC fault output connected to the PWM is not the COMPE bit. Thus the Fault
Mode (FMOD) within the PWM configuration must be FMOD = 1.
To prevent any single software error that may corrupt ADC behavior, certain address spaces
can be write-protected by setting the WPEN bit in the
(ADC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the ADC Write Pro-
tect Status Register (ADC_WPSR) is set and the field WPVSRC indicates in which register the
write access has been attempted.
The WPVS flag is reset by writing the ADC Write Protect Mode Register (ADC_WPMR) with the
appropriate access key, WPKEY.
The protected registers are:
“ADC Mode Register” on page 1043
“ADC Channel Sequence 1 Register” on page 1046
“ADC Channel Sequence 2 Register” on page 1047
“ADC Channel Enable Register” on page 1048
“ADC Channel Disable Register” on page 1049
“ADC Extended Mode Register” on page 1057
“ADC Compare Window Register” on page 1058
“ADC Channel Gain Register” on page 1059
“ADC Channel Offset Register” on page 1060
“ADC Analog Control Register” on page 1062
“ADC Write Protect Mode Register”
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11

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