SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 108

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.6.5.1
108
108
SAM4S
SAM4S
ADD, ADC, SUB, SBC, and RSB
Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.
Syntax
where:
op
S
cond
Rd
Rn
Operand2
imm12
Operation
The
The
The
The
the result is reduced by one.
The
the wide range of options for
Use
See also
Note:
Restrictions
In these instructions:
Operand2
Rd
Rn
Rd
op{S}{cond} {Rd,} Rn, Operand2
op{cond} {Rd,} Rn, #imm12
ADD
ADC
SUB
SBC
RSB
ADC
– any shift in
– the user must not specify the S suffix
can be SP only in
can be SP only in
can be PC only in the
Rn
Rm
ADDW
syntax that uses the
instruction subtracts the value of
instruction adds the value of
instruction adds the values in
instruction subtracts the value in
instruction subtracts the value of
and
“ADR”
must also be SP
must not be PC and must not be SP
must not be SP and must not be PC
SBC
is equivalent to the
is one of:
ADD
ADC
SUB
SBC
RSB
is an optional suffix. If
of the operation, see
is an optional condition code, see
is the destination register. If
is the register holding the first operand.
is a flexible second operand. See
is any value in the range 0-4095.
.
to synthesize multiword arithmetic, see Multiword arithmetic examples on.
Subtract.
Subtract with Carry.
Reverse Subtract.
Add.
Add with Carry.
Operand2
ADD
ADD
imm12
must be limited to a maximum of 3 bits using
ADD{cond} PC, PC, Rm
and
and
Operand2
ADD
operand.
SUB
SUB
“Conditional Execution”
S
syntax that uses the
, and only with the additional restrictions:
.
is specified, the condition code flags are updated on the result
Operand2
Rn
Rd
and
Operand2
Rn
Operand2
is omitted, the destination register is
from the value of
or
“Flexible Second Operand”
Operand2
“Conditional Execution”
instruction where:
imm12
or
from the value in
imm12
, together with the carry flag.
; ADD and SUB only
to the value in
imm12
.
from the value in
operand.
Operand2
.
SUBW
Rn
Rn
. This is useful because of
.
. If the carry flag is clear,
for details of the options.
LSL
is equivalent to the
Rn
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Rn
.
.
SUB

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