SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 238

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.11 Memory Protection Unit (MPU)
Table 11-34. Memory Attributes Summary
11.11.1
238
238
Memory Type
Strongly- ordered
Device
Normal
SAM4S
SAM4S
MPU Access Permission Attributes
Shareability
-
Shared
Non-shared
Shared
Non-shared
The MPU divides the memory map into a number of regions, and defines the location, size,
access permissions, and memory attributes of each region. It supports:
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4
MPU defines:
When memory regions overlap, a memory access is affected by the attributes of the region with
the highest number. For example, the attributes for region 7 take precedence over the attributes
of any region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but
is accessible from privileged software only.
The Cortex-M4 MPU memory map is unified. This means that instruction accesses and data
accesses have the same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates
a memory management fault. This causes a fault exception, and might cause the termination of
the process in an OS environment.
In an OS environment, the kernel can update the MPU region setting dynamically based on the
process to be executed. Typically, an embedded OS uses the MPU for memory protection.
The configuration of MPU regions is based on memory types (see
Attributes”
Table 11-34
behavior attributes that are not relevant to most microcontroller implementations. See
figuration for a Microcontroller”
This section describes the MPU access permission attributes. The access permission bits (TEX,
C, B, S, AP, and XN) of the MPU_RASR control the access to the corresponding memory
region. If an access is made to an area of memory without the required permissions, then the
MPU generates a permission fault.
• independent attribute settings for each region
• overlapping regions
• export of memory attributes to the system.
• eight separate memory regions, 0-7
• a background region.
Other Attributes
-
-
-
).
shows the possible MPU region attributes. These include Share ability and cache
for guidelines for programming such an implementation.
Description
All accesses to Strongly-ordered memory occur in program order. All
Strongly-ordered regions are assumed to be shared.
Memory-mapped peripherals that several processors share.
Memory-mapped peripherals that only a single processor uses.
Normal memory that is shared between several processors.
Normal memory that only a single processor uses.
“Memory Regions, Types and
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
“MPU Con-

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