SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 1128

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
41.11.6
41.11.6.1
Table 41-50. SMC Read Signals - NRD Controlled (READ_MODE = 1)
1128
Symbol
SMC
SMC
SMC
SMC
SMC
SMC
SMC
1
2
3
4
5
6
7
SAM4S
SMC Timings
Parameter
Data Setup before NRD High
Data Hold after NRD High
Data Setup before NRD High
Data Hold after NRD High
NCS low before NRD High
NRD Pulse Width
Read Timings
A0 - A22 Valid before NRD High
VDDIO Supply
Figure 41-25. Min and Max Access Time of Output Signals
SMC Timings are given with the following conditions.
VDDIO = 1.62V @ 30 pF
VDDIO = 3.3 V @ 50 pF
Timings are given assuming a capacitance load on data, control and address pads:
In the following tables t
HOLD or NO HOLD SETTINGS (nrd hold ≠ 0, nrd hold = 0)
NO HOLD SETTINGS (nrd hold = 0)
TK (CKI =0)
TK (CKI =1)
HOLD SETTINGS (nrd hold ≠ 0)
nrd pulse - ncs
(nrd setup +
(nrd setup +
nrd pulse) *
t
TF/TD
CPMCK
t
nrd pulse *
CPMCK
rd setup) *
CPMCK
t
CPMCK
1.8V
16.5
12.6
0
0
- 3.5
is MCK period. Timing extraction
- 3.1
(2)
- 3
Min
nrd pulse - ncs
(nrd setup +
(nrd setup +
t
nrd pulse)*
nrd pulse *
rd setup) *
CPMCK
t
t
CPMCK
CPMCK
3.3V
14.7
10.8
SSC
0
0
SSC
- 3.2
(3)
- 3
- 3
0max
0min
1.8V
TBD
TBD
TBD
TBD
TBD
TBD
TBD
(2)
Max
3.3V
TBD
TBD
TBD
TBD
TBD
TBD
TBD
11100A–ATARM–28-Oct-11
(3)
Units
ns
ns
ns
ns
ns
ns
ns

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