SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 208
SAM4S16C
Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Specifications of SAM4S16C
Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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System Control Block (SCB)
SAM4S
SAM4S
The System Control Block (SCB) provides system implementation information, and system con-
trol. This includes configuration, control, and reporting of the system exceptions.
Ensure that the software uses aligned accesses of the correct size to access the system control
block registers:
The processor does not support unaligned accesses to system control block registers.
In a fault handler, to determine the true faulting address:
The software must follow this sequence because another higher priority exception might change
the SCB_MMFAR or SCB_BFAR value. For example, if a higher priority handler preempts the
current fault handler, the other fault might change the SCB_MMFAR or SCB_BFAR value.
• except for the SCB_CFSR and SCB_SHPR1-SCB_SHPR3 registers, it must use aligned
• for the SCB_CFSR and SCB_SHPR1-SCB_SHPR3 registers, it can use byte or aligned
1. Read and save the MMFAR or SCB_BFAR value.
2. Read the MMARVALID bit in the MMFSR subregister, or the BFARVALID bit in the
word accesses
halfword or word accesses.
BFSR subregister. The SCB_MMFAR or SCB_BFAR address is valid only if this bit is 1.
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
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