SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 923

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
36.6.5.6
36.6.5.7
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Interrupts
Write Protect Registers
Figure 36-19. Synchronized Update of Comparison Values and Configurations
Depending on the interrupt mask in the PWM_IMR1 and PWM_IMR2 registers, an interrupt can
be generated at the end of the corresponding channel period (CHIDx in the PWM_ISR1 regis-
ter), after a fault event (FCHIDx in the PWM_ISR1 register), after a comparison match (CMPMx
in the PWM_ISR2 register), after a comparison update (CMPUx in the PWM_ISR2 register) or
according to the transfer mode of the synchronous channels (WRDY, ENDTX, TXBUFE and
UNRE in the PWM_ISR2 register).
If the interrupt is generated by the flags CHIDx or FCHIDx, the interrupt remains active until a
read operation in the PWM_ISR1 register occurs.
If the interrupt is generated by the flags WRDY or UNRE or CMPMx or CMPUx, the interrupt
remains active until a read operation in the PWM_ISR2 register occurs.
A channel interrupt is enabled by setting the corresponding bit in the PWM_IER1 and
PWM_IER2 registers. A channel interrupt is disabled by setting the corresponding bit in the
PWM_IDR1 and PWM_IDR2 registers.
To prevent any single software error that may corrupt PWM behavior, the registers listed below
can be write-protected by writing the field WPCMD in the
on page 957
• Register group 0:
• Register group 1:
• Register group 2:
“PWM Clock Register” on page 928
“PWM Disable Register” on page 930
“PWM Sync Channels Mode Register” on page 936
End of channel0 PWM period and
end of Comparison Update Period and
and PWM_CMPMx written
End of channel0 PWM period and
end of Comparison Update Period
(PWM_WPCR). They are divided into 6 groups:
PWM_CMPVUPDx Value
Comparison Value
for comparison x
PWM_CMPVx
User's Writing
“PWM Write Protect Control Register”
PWM_CMPMUPDx Value
Comparison configuration
for comparison x
User's Writing
PWM_CMPMx
SAM4S
SAM4S
923
923

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