SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 84

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.6.3.3
84
84
Constant
Instruction Substitution
Register with Optional Shift
SAM4S
SAM4S
Flexible Second Operand
Many general data processing instructions have a flexible second operand. This is shown as
Operand2 in the descriptions of the syntax of each instruction.
Operand2 can be a:
Specify an Operand2 constant in the form:
where constant can be:
Note:
In addition, in a small number of instructions, constant can take a wider range of values.
These are described in the individual instruction descriptions.
When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS,
EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is
greater than 255 and can be produced by shifting an 8-bit value. These instructions do not affect
the carry flag if Operand2 is any other constant.
The assembler might be able to produce an equivalent instruction in cases where the user spec-
ifies a constant that is not permitted. For example, an assembler might assemble the instruction
CMP Rd, #0xFFFFFFFE as the equivalent instruction CMN Rd, #0x2.
Specify an Operand2 register in the form:
where:
Rm
shift
• any constant that can be produced by shifting an 8-bit value left by any number of bits within
• any constant of the form 0x00XY00XY
• any constant of the form 0xXY00XY00
• any constant of the form 0xXYXYXYXY.
“Constant”
“Register with Optional Shift”
a 32-bit word
#constant
Rm {, shift}
ASR #n
LSL #n
LSR #n
ROR #n
RRX
-
In the constants shown above, X and Y are hexadecimal digits.
is the register holding the data for the second operand.
is an optional shift to be applied to Rm. It can be one of:
arithmetic shift right n bits, 1 ≤ n ≤ 32.
logical shift left n bits, 1 ≤ n ≤ 31.
logical shift right n bits, 1 ≤ n ≤ 32.
rotate right n bits, 1 ≤ n ≤ 31.
rotate right one bit, with extend.
if omitted, no shift occurs, equivalent to LSL #0.
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11

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