SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 98

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.6.4.4
98
98
STRBTEQ
LDRHT
SAM4S
SAM4S
LDR and STR, unprivileged
R4, [R7]
R2, [R2, #8]
Load and Store with unprivileged access.
Syntax
where:
op
type is one of:
cond
Rt
Rn
offset
Operation
These load and store instructions perform the same function as the memory access instructions
with immediate offset, see
instructions have only unprivileged access even when used in privileged software.
When used in unprivileged software, these instructions behave in exactly the same way as nor-
mal memory access instructions with immediate offset.
Restrictions
In these instructions:
Condition Flags
These instructions do not change the flags.
Examples
• Rn must not be PC
• Rt must not be SP and must not be PC.
op{type}T{cond} Rt, [Rn {, #offset}]
LDR
STR
B
SB
H
SH
-
; Conditionally store least significant byte in
; R4 to an address in R7, with unprivileged access
; Load halfword value from an address equal to
; sum of R2 and 8 into R2, with unprivileged access
is one of:
Load Register.
Store Register.
unsigned byte, zero extend to 32 bits on loads.
signed byte, sign extend to 32 bits (LDR only).
unsigned halfword, zero extend to 32 bits on loads.
signed halfword, sign extend to 32 bits (LDR only).
omit, for word.
is an optional condition code, see
is the register to load or store.
is the register on which the memory address is based.
is an offset from Rn and can be 0 to 255.
If offset is omitted, the address is the value in Rn.
“LDR and STR, Immediate Offset”
“Conditional Execution”
; immediate offset
. The difference is that these
.
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11

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