SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 57

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.4.2.2
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Memory Types
Additional Memory Attributes
Memory System Ordering of Memory Accesses
The different ordering requirements for Device and Strongly-ordered memory mean that the
memory system can buffer a write to Device memory, but must not buffer a write to Strongly-
ordered memory.
For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing this does not affect the behavior of the instruction sequence. Nor-
mally, if correct program execution depends on two memory accesses completing in program
order, the software must insert a memory barrier instruction between the memory access
instructions, see
However, the memory system does guarantee some ordering of accesses to Device and
Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs before
A2 in program order, the ordering of the memory accesses is described below.
Table 11-3.
Where:
A1
Normal Access
Device access, non-shareable
Device access, shareable
Strongly-ordered access
• Normal
• Device
• Strongly-ordered
• Shareable
• Execute Never (XN)
The processor can re-order transactions for efficiency, or perform speculative reads.
The processor preserves transaction order relative to other transactions to Device or
Strongly-ordered memory.
The processor preserves transaction order relative to all other transactions.
For a shareable memory region, the memory system provides data synchronization between
bus masters in a system with multiple bus masters, for example, a processor with a DMA
controller.
Strongly-ordered memory is always shareable.
If multiple bus masters can access a non-shareable memory region, the software must
ensure data coherency between the bus masters.
Means the processor prevents instruction accesses. A fault exception is generated only on
execution of an instruction executed from an XN region.
Ordering of the Memory Accesses Caused by Two Instructions
“Software Ordering of Memory Accesses”
A2
Access
Normal
Non-shareable
<
<
Device Access
.
Shareable
<
<
Strongly-
ordered
Access
SAM4S
SAM4S
<
<
<
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