SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 345

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Table 19-3.
19.4.3.2
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Symbol
FL_ID
FL_SIZE
FL_PAGE_SIZE
FL_NB_PLANE
FL_PLANE[0]
...
FL_PLANE[FL_NB_PLANE-1]
FL_NB_LOCK
FL_LOCK[0]
...
Write Commands
Flash Descriptor Definition
reads of the EEFC_FRR register provide the following word of the descriptor. If extra read oper-
ations to the EEFC_FRR register are done after the last word of the descriptor has been
returned, then the EEFC_FRR register value is 0 until the next valid command.
Several commands can be used to program the Flash.
Flash technology requires that an erase be done before programming. The full memory plane
can be erased at the same time, or several pages can be erased at the same time (refer to
ure 19-6, "Example of Partial Page
page erase can be automatically done before a page write using EWP or EWPL commands.
After programming, the page (the whole lock region) can be locked to prevent miscellaneous
write or erase sequences. The lock bit can be automatically set after page programming using
WPL or EWPL commands.
Data to be written are stored in an internal latch buffer. The size of the latch buffer corresponds
to the page size. The latch buffer wraps around within the internal memory area address space
and is repeated as many times as the number of pages within this address space.
Note:
Write operations are performed in a number of wait states equal to the number of wait states for
read operations.
Data are written to the latch buffer before the programming command is written to the Flash
Command Register EEFC_FCR. The sequence is as follows:
• Write the full page, at any page address, within the internal memory area address space.
• Programming starts as soon as the page number and the programming command are written
• When programming is completed, the FRDY bit in the Flash Programming Status Register
to the Flash Command Register. The FRDY bit in the Flash Programming Status Register
(EEFC_FSR) is automatically cleared.
(EEFC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in EEFC_FMR,
the corresponding interrupt line of the NVIC is activated.
Writing of 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.
Word Index
0
1
2
3
4
4 + FL_NB_PLANE - 1
4 + FL_NB_PLANE + 1
4 + FL_NB_PLANE
Programming", and the paragraph below the figure.). Also, a
Description
Flash Interface Description
Flash size in bytes
Page size in bytes
Number of planes.
Number of bytes in the first plane.
Number of bytes in the last plane.
Number of lock bits. A bit is associated
with a lock region. A lock bit is used to
prevent write or erase operations in the
lock region.
Number of bytes in the first lock region.
SAM4S
SAM4S
Fig-
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