SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 649

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
30.7.5
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Write Protected Registers
Figure 30-12. Slave Mode Functional Bloc Diagram
To prevent any single software error that may corrupt SPI behavior, the registers listed below
can be write-protected by setting the SPIWPEN bit in the SPI Write Protection Mode Register
(SPI_WPMR).
If a write access in a write-protected register is detected, then the SPIWPVS flag in the SPI
Write Protection Status Register (SPI_WPSR) is set and the field SPIWPVSRC indicates in
which register the write access has been attempted.
The SPIWPVS flag is automatically reset after reading the SPI Write Protection Status Register
(SPI_WPSR).
List of the write-protected registers:
Section 30.8.2 ”SPI Mode Register”
Section 30.8.9 ”SPI Chip Select Register”
SPCK
MOSI
NSS
SPIDIS
SPIEN
SPIENS
SPI_CSR0
LSB
NCPHA
CPOL
BITS
Shift Register
Clock
SPI
SPI_RDR
SPI_TDR
RD
TD
MSB
OVRES
RDRF
TDRE
SAM4S
SAM4S
MISO
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