SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 167

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.6.8.1
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
PKHBT and PKHTB
Pack Halfword
Syntax
op{cond} {Rd}, Rn, Rm {, LSL #imm}
op{cond} {Rd}, Rn, Rm {, ASR #imm}
where:
op
cond
Rd
Rn
Rm
imm
Operation
The PKHBT
The
Restrictions
Rd
Condition Flags
This instruction does not change the flags.
Examples
PKHBT R3, R4, R5 LSL #0 ; Writes bottom halfword of R4 to bottom halfword of
PKHTB R4, R0, R2 ASR #1 ; Writes R2 shifted right by 1 bit to bottom halfword
1. Writes the value of the bottom halfword of the first operand to the bottom halfword of
2. If shifted, the shifted value of the second operand is written to the top halfword of the
1. Writes the value of the top halfword of the first operand to the top halfword of the desti-
2. If shifted, the shifted value of the second operand is written to the bottom halfword of
must not be SP and must not be PC.
PKHTB
the destination register.
destination register.
nation register.
the destination register.
instruction:
instruction:
is one of:
PKHBT
PKHTB
is an optional condition code, see
is the destination register.
is the first operand register.
is the second operand register holding the value to be optionally shifted.
is the shift length. The type of shift length depends on the instruction:
For
LSL
For
ASR
a shift of 32-bits is encoded as
a left shift with a shift length from 1 to 31, 0 means no shift.
PKHBT
PKHTB
an arithmetic shift right with a shift length from 1 to 32,
Pack Halfword, bottom and top with shift.
Pack Halfword, top and bottom with shift.
; halfword of R4.
; R3, writes top halfword of R5, unshifted, to top
; halfword of R3
; of R4, and writes top halfword of R0 to top
0b00000
“Conditional Execution”
.
.
SAM4S
SAM4S
167
167

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