SAM4S16C

Manufacturer Part NumberSAM4S16C
ManufacturerAtmel Corporation
SAM4S16C datasheets
 

Specifications of SAM4S16C

Flash (kbytes)1024 KbytesPin Count100
# Of Touch Channels32Hardware Qtouch AcquisitionNo
Max I/o Pins79Ext Interrupts79
Usb Transceiver1Quadrature Decoder Channels2
Usb SpeedFull SpeedUsb InterfaceDevice
Spi3Twi (i2c)2
Uart4Ssc1
Sd / Emmc1Graphic LcdNo
Video DecoderNoCamera InterfaceNo
Adc Channels16Adc Resolution (bits)12
Adc Speed (ksps)1000Analog Comparators1
Resistive Touch ScreenNoDac Channels2
Dac Resolution (bits)12Temp. SensorYes
Crypto EngineNoSram (kbytes)128
Self Program MemoryYESExternal Bus Interface1
Dram MemoryNoNand InterfaceYes
PicopowerNoTemp. Range (deg C)-40 to 85
I/o Supply Class1.8/3.3Operating Voltage (vcc)1.62 to 3.6
FpuNoMpu / MmuYes / No
Timers6Output Compare Channels6
Input Capture Channels6Pwm Channels4
32khz RtcYesCalibrated Rc OscillatorYes
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30.7.3.10
Mode Fault Detection
A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven
by an external master on the NPCS0/NSS signal. In this case, multi-master configuration,
NPCS0, MOSI, MISO and SPCK pins must be configured in open drain (through the PIO control-
ler). When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read
and the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR
(Control Register) at 1.
By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault
detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR).
30.7.4
SPI Slave Mode
When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI
clock pin (SPCK).
The SPI waits for NSS to go active before receiving the serial clock from an external master.
When NSS falls, the clock is validated on the serializer, which processes the number of bits
defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed
following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the
SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no
effect when the SPI is programmed in Slave Mode.
The bits are shifted out on the MISO line and sampled on the MOSI line.
(For more information on BITS field, see also, the
“SPI Chip Select Register” on page
When all the bits are processed, the received data is transferred in the Receive Data Register
and the RDRF bit rises. If the SPI_RDR (Receive Data Register) has not been read before new
data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data
is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit.
When a transfer starts, the data shifted out is the data present in the Shift Register. If no data
has been written in the Transmit Data Register (SPI_TDR), the last data received is transferred.
If no data has been received since the last reset, all bits are transmitted low, as the Shift Regis-
ter resets at 0.
When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the
TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls
and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in
SPI_TDR is transferred in the Shift Register and the TDRE bit rises. This enables frequent
updates of critical variables with single transfers.
Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no
character is ready to be transmitted, i.e. no character has been written in SPI_TDR since the last
load from SPI_TDR to the Shift Register, the Shift Register is not modified and the last received
character is retransmitted. In this case the Underrun Error Status Flag (UNDES) is set in the
SPI_SR.
Figure 30-12
SAM4S
SAM4S
648
648
661.)
shows a block diagram of the SPI when operating in Slave Mode.
(Note:)
below the register table;
Section 30.8.9
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11