SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 121

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.6.5.11
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
SHASX and SHSAX
Signed Halving Add and Subtract with Exchange and Signed Halving Subtract and Add with
Exchange.
Syntax
op{cond} {Rd}, Rn, Rm
where:
op
cond
Rd
Rn, Rm
Operation
The
The
Restrictions
Do not use SP and do not use PC
Condition Flags
These instructions do not affect the condition code flags.
Examples
SHASX
SHSAX
1. Adds the top halfword of the first operand with the bottom halfword of the second
2. Writes the halfword result of the addition to the top halfword of the destination register,
3. Subtracts the top halfword of the second operand from the bottom highword of the first
4. Writes the halfword result of the division in the bottom halfword of the destination regis-
1. Subtracts the bottom halfword of the second operand from the top highword of the first
2. Writes the halfword result of the addition to the bottom halfword of the destination regis-
3. Adds the bottom halfword of the first operand with the top halfword of the second
4. Writes the halfword result of the division in the top halfword of the destination register,
SHASX
SHSAX
operand.
shifted by one bit to the right causing a divide by two, or halving.
operand.
ter, shifted by one bit to the right causing a divide by two, or halving.
operand.
ter, shifted by one bit to the right causing a divide by two, or halving.
operand.
shifted by one bit to the right causing a divide by two, or halving.
R7, R4, R2
R0, R3, R5
instruction:
instruction:
is any of:
SHASX
SHSAX
is an optional condition code, see
is the destination register.
are registers holding the first and second operands.
Add and Subtract with Exchange and Halving.
Subtract and Add with Exchange and Halving.
; Adds top halfword of R4 to bottom halfword of R2
; and writes halved result to top halfword of R7
; Subtracts top halfword of R2 from bottom halfword of
; R4 and writes halved result to bottom halfword of R7
; Subtracts bottom halfword of R5 from top halfword
.
“Conditional Execution”
.
SAM4S
SAM4S
121
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