SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 969

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
36.7.40
Name:
Address:
Access:
This register can only be written if the bits WPSWS3 and WPHWS3 are cleared in
page
This register acts as a double buffer for the CPRD value. This prevents an unexpected waveform when modifying the
waveform period.
Only the first 16 bits (channel counter size) are significant.
• CPRDUPD: Channel Period Update
If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be
calculated:
If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can
be calculated:
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
959.
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
31
23
15
7
(
------------------------------------------------------- -
(
------------------------------------------------------------------ -
64, 128, 256, 512, or 1024). The resulting period formula will be:
respectively:
64, 128, 256, 512, or 1024). The resulting period formula will be:
respectively:
(
---------------------------------------------
2
2
X
(
-------------------------------------------------------- -
CRPDUPD
×
×
×
PWM Channel Period Update Register
X
CPRDUPD
CPRDUPD
MCK
×
PWM_CPRDUPDx [x=0..3]
0x40020210 [0], 0x40020230 [1], 0x40020250 [2], 0x40020270 [3]
Write-only
MCK
CPRDUPD
MCK
MCK
×
30
22
14
DIVA
6
)
×
DIVA
)
)
or
)
or
(
-------------------------------------------------------- -
CRPDUPD
(
------------------------------------------------------------------ -
2
×
29
21
13
5
CPRDUPD
MCK
MCK
×
DIVB
×
)
DIVB
28
20
12
4
CPRDUPD
CPRDUPD
CPRDUPD
)
27
19
11
3
“PWM Write Protect Status Register” on
26
18
10
2
25
17
9
1
SAM4S
SAM4S
24
16
8
0
969
969

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