SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 913

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Figure 36-11. Method 2 (UPDM = 1)
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Method 3: Automatic write of duty-cycle values and automatic trigger of the update
CDTYUPD
UPRUPD
UPRCNT
CCNT0
WRDY
CDTY
UPR
0x0
0x20
0x1
0x1
0x20
0x1
In this mode, the update of the duty cycle values is made automatically by the Peripheral DMA
Controller (PDC). The update of the period value, the dead-time values and the update period
value must be done by writing in their respective update registers with the CPU (respectively
PWM_CPRDUPDx, PWM_DTUPDx and PWM_SCUPUPD).
To trigger the update of the period value and the dead-time values, the user must use the bit
UPDULOCK which allows to update synchronously (at the same PWM period) the synchronous
channels:
After writing the UPDULOCK bit to 1, it is held at this value until the update occurs, then it is read 0.
The update of the duty-cycle values and the update period value is triggered automatically after
an update period.
To configure the automatic update, the user must define a value for the Update Period by the
field UPR in the
troller waits UPR+1 periods of synchronous channels before updating automatically the duty
values and the update period value.
6. Set UPDULOCK to 1 in PWM_SCUC.
7. The update of these registers will occur at the beginning of the next PWM period. At
8. If an update of the duty-cycle values and/or the update period is required, check first
9. Write registers that need to be updated (PWM_CDTYUPDx, PWM_SCUPUPD).
10. The update of these registers will occur at the next PWM period of the synchronous
• If the bit UPDULOCK is set to 1, the update is done at the next PWM period of the
• If the UPDULOCK bit is not set to 1, the update is locked and cannot be performed.
synchronous channels.
this moment the bit UPDULOCK is reset, go to
that write of new update values is possible by polling the flag WRDY (or by waiting for
the corresponding interrupt) in the PWM_ISR2 register.
channels when the Update Period is elapsed. Go to
0x0
0x40
0x1
“PWM Sync Channels Update Period Register”
0x0
0x40
0x3
0x1
0x3
0x0
0x60
0x1
0x2
Step 5.
Step 8.
0x3
for new values.
(PWM_SCUP). The PWM con-
0x0
0x60
for new values.
0x1
0x2
SAM4S
SAM4S
913
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