SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 321

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
17.4.4
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Supply Monitor
consumption as the voltage regulator input (VDDIN) is shared with the ADC and DAC. This is
done through ONREG bit in SUPC_MR.
The Supply Controller embeds a supply monitor which is located in the VDDIO Power Supply
and which monitors VDDIO power supply.
The supply monitor can be used to prevent the processor from falling into an unpredictable state
if the Main power supply drops below a certain level.
The threshold of the supply monitor is programmable. It can be selected from 1.9V to 3.4V by
steps of 100 mV. This threshold is programmed in the SMTH field of the Supply Controller Sup-
ply Monitor Mode Register (SUPC_SMMR).
The supply monitor can also be enabled during one slow clock period on every one of either 32,
256 or 2048 slow clock periods, according to the choice of the user. This can be configured by
programming the SMSMPL field in SUPC_SMMR.
Enabling the supply monitor for such reduced times allows to divide the typical supply monitor
power consumption respectively by factors of 32, 256 or 2048, if the user does not need a con-
tinuous monitoring of the VDDIO power supply.
A supply monitor detection can either generate a reset of the core power supply or a wake up of
the core power supply. Generating a core reset when a supply monitor detection occurs is
enabled by writing the SMRSTEN bit to 1 in SUPC_SMMR.
Waking up the core power supply when a supply monitor detection occurs can be enabled by
programming the SMEN bit to 1 in the Supply Controller Wake Up Mode Register
(SUPC_WUMR).
The Supply Controller provides two status bits in the Supply Controller Status Register for the
supply monitor which allows to determine whether the last wake up was due to the supply
monitor:
The SMS bit can generate an interrupt if the SMIEN bit is set to 1 in the Supply Controller Supply
Monitor Mode Register (SUPC_SMMR).
• The SMOS bit provides real time information, which is updated at each measurement cycle
• The SMS bit provides saved information and shows a supply monitor detection has occurred
or updated at each Slow Clock cycle, if the measurement is continuous.
since the last read of SUPC_SR.
SAM4S
SAM4S
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