SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 99

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.6.4.5
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
LDR, PC-relative
Load register from memory.
Syntax
where:
type
cond
Rt
Rt2
label
Operation
LDR loads a register with a value from a PC-relative memory address. The memory address is
specified by a label or by an offset from the PC.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and half-
words can either be signed or unsigned. See
label must be within a limited range of the current instruction. The table below shows the possi-
ble offsets between label and the PC.
Table 11-19. Offset Ranges
The user might have to use the .W suffix to get the maximum offset range. See
Width Selection”
Restrictions
In these instructions:
When Rt is PC in a word load instruction:
Instruction Type
Word, halfword, signed halfword, byte, signed byte
Two words
• Rt can be SP or PC only for word loads
• Rt2 must not be SP and must not be PC
• Rt must be different from Rt2.
• bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this
halfword-aligned address
LDR{type}{cond} Rt, label
LDRD{cond} Rt, Rt2, label
B
SB
H
SH
-
is one of:
unsigned byte, zero extend to 32 bits.
signed byte, sign extend to 32 bits.
unsigned halfword, zero extend to 32 bits.
signed halfword, sign extend to 32 bits.
omit, for word.
is an optional condition code, see
is the register to load or store.
is the second register to load or store.
is a PC-relative expression. See
.
“Address Alignment”
; Load two words
“PC-relative Expressions”
“Conditional Execution”
Offset Range
-4095 to 4095
-1020 to 1020
.
.
.
SAM4S
SAM4S
“Instruction
99
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