SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 59

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.4.2.4
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Instruction Prefetch And Branch Prediction
DMB
DSB
ISB
Software Ordering of Memory Accesses
Table 11-5.
Notes:
The Cortex-M4 processor:
The order of instructions in the program flow does not always guarantee the order of the corre-
sponding memory transactions. This is because:
“Memory System Ordering of Memory Accesses”
tem guarantees the order of memory accesses. Otherwise, if the order of memory accesses is
critical, the software must include memory barrier instructions to force that ordering. The proces-
sor provides the following memory barrier instructions:
The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions com-
plete before subsequent memory transactions. See
The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transac-
tions complete before subsequent instructions execute. See
The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory
transactions is recognizable by subsequent instructions. See
Address Range
0x60000000-
0x7FFFFFFF
0x80000000-
0x9FFFFFFF
0xA0000000-
0xBFFFFFFF
0xC0000000-
0xDFFFFFFF
0xE0000000-
0xE00FFFFF
0xE0100000-
0xFFFFFFFF
• prefetches instructions ahead of execution
• speculatively prefetches from branch target addresses.
• the processor can reorder some memory accesses to improve efficiency, providing this does
• the processor has multiple bus interfaces
• memory or devices in the memory map have different wait states
• some memory accesses are buffered or speculative.
not affect the behavior of the instruction sequence.
1. See
2. WT = Write through, no write allocate. WBWA = Write back, write allocate. See the
for more information.
Memory Region Shareability Policies (Continued)
“Memory Regions, Types and Attributes”
Memory Region
External RAM
External device
Private Peripheral
Bus
Vendor-specific
device
Memory Type
Normal
Device
Strongly- ordered
Device
(1)
(1)
(1)
describes the cases where the memory sys-
“DMB”
for more information.
(1)
.
“DSB”
“ISB”
Shareability
-
Shareable
Non-shareable
Shareable
-
.
.
(1)
(1)
(1)
WBWA
WT
-
-
-
SAM4S
SAM4S
(2)
“Glossary”
(2)
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