SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 484

no-image

SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
26.2.3
Figure 26-5. General Clock Block Diagram
26.2.4
484
484
XOUT32
(Supply C ontroller)
XOUT
XIN32
XIN
XTALSEL
SAM4S
SAM4S
Block Diagram
Master Clock Controller
Clock G ene rator
RC Oscillator
Management
Embedded
32 kH z R C
4/8/12 MHz
Embedded
32768 H z
Oscilla tor
Oscilla tor
Resonator
Status
3-20 MH z
Oscilla tor
Ceramic
Crystal
Controller
Crystal
Power
Fast
or
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is
the clock provided to all the peripherals.
The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting
the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock
saves power consumption of the PLLs.
The Master Clock Controller is made up of a clock selector and a prescaler.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in
PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the
selected clock between 1 and 64, and the division by 3. The PRES field in PMC_MCKR pro-
grams the prescaler.
Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in
PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can
trigger an interrupt to the processor. This feature is useful when switching from a high-speed
clock to a lower one to inform the software when the change is actually done.
Control
0
1
0
1
MOSCSEL
PLLB and
PLLA and
Divider /2
PLLBDIV2
PLLADIV2
Divider /2
PLLA Clock
PLLA CK
PLLB Clock
PLLBCK
Main Clock
MAINCK
Sl ow Clock
SLCK
SLCK
MAINCK
PLLBCK
PLLA CK
CSS
Master Clock Controller
PLLA CK
PLLBCK
PLLA CK
MCK
MAINCK
PLLBCK
SLCK
(P MC_MCKR)
/1,/2,/3,/4,/8,
/16,/32,/64
PRES
Prescaler
USBS
CSS
USB Clock C ontroller (PMC_USB)
Programmable Clock Controller
/1,/2,/4,/8,
/16,/32,/64
/1,/2,/3,...,/16
(P MC_PCKx)
Prescaler
Divider
PRES
USBDI V
Peripherals
Clock C ontroller
(PMC_PCERx)
Sleep M ode
Processor
Controller
Divider
ON/OFF
Clock
ON/OFF
/8
ON/OFF
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Free running clock
Processor clock c
Master clock
USB Clock
HCLK
int
SysTick
FCLK
MCK
periph_clk[..]
pck[..]
UDPCK

Related parts for SAM4S16C