SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 689

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
31.7.3.8
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Parity
The USART supports five parity modes selected by programming the PAR field in the Mode
Register (US_MR). The PAR field also enables the Multidrop mode, see
page
If even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a num-
ber of 1s in the character data bit is even, and to 1 if the number of 1s is odd. Accordingly, the
receiver parity checker counts the number of received 1s and reports a parity error if the sam-
pled parity bit does not correspond. If odd parity is selected, the parity generator of the
transmitter drives the parity bit to 1 if a number of 1s in the character data bit is even, and to 0 if
the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received
1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is
used, the parity generator of the transmitter drives the parity bit to 1 for all characters. The
receiver parity checker reports an error if the parity bit is sampled to 0. If the space parity is
used, the parity generator of the transmitter drives the parity bit to 0 for all characters. The
receiver parity checker reports an error if the parity bit is sampled to 1. If parity is disabled, the
transmitter does not generate any parity bit and the receiver does not report any parity error.
Table 31-9
depending on the configuration of the USART. Because there are two bits to 1, 1 bit is added
when a parity is odd, or 0 is added when a parity is even.
Table 31-9.
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status
Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with
the RSTSTA bit to 1.
Character
690. Even and odd parity bit generation and error detection are supported.
A
A
A
A
A
shows an example of the parity bit for the character 0x41 (character ASCII “A”)
Parity Bit Examples
Figure 31-22
Hexa
0x41
0x41
0x41
0x41
0x41
illustrates the parity bit status setting and clearing.
0100 0001
0100 0001
0100 0001
0100 0001
0100 0001
Binary
Parity Bit
None
1
0
1
0
“Multidrop Mode” on
Parity Mode
Space
SAM4S
SAM4S
None
Even
Mark
Odd
689
689

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