SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 120

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.6.5.10
120
120
SAM4S
SAM4S
SHADD16 and SHADD8
Signed Halving Add 16 and Signed Halving Add 8
Syntax
op{cond}{Rd,} Rn, Rm
where:
op
cond
Rd
Rn
Rm
Operation
Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the
result to the destination register:
The
The
Restrictions
Do not use SP and do not use PC
Condition Flags
These instructions do not change the flags.
Examples
SHADD16 R1, R0
SHADD8 R4, R0, R5; Adds bytes of R0 to corresponding byte in R5 and
1. Adds each halfword from the first operand to the corresponding halfword of the second
2. Shuffles the result by one bit to the right, halving the data.
3. Writes the halfword results in the destination register.
1. Adds each byte of the first operand to the corresponding byte of the second operand.
2. Shuffles the result by one bit to the right, halving the data.
3. Writes the byte results in the destination register.
SHADD16
SHADDB8
operand.
instruction:
instruction:
is any of:
SHADD16
SHADD8
is an optional condition code, see
is the destination register.
is the first operand register.
is the second operand register.
; Adds halfwords in R0 to corresponding halfword of R1 and
; writes halved result to corresponding halfword in R1
; writes halved result to corresponding byte in R4.
Signed Halving Add 8
Signed Halving Add 16
.
“Conditional Execution”
.
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11

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