SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 481

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
26.1.6
26.1.6.1
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Divider and PLL Block
Divider and Phase Lock Loop Programming
The device features two Divider/PLL Blocks that permit a wide range of frequencies to be
selected on either the master clock, the processor clock or the programmable clock outputs.
Additionally, they provide a 48 MHz signal to the embedded USB device port regardless of the
frequency of the main clock.
Figure 26-4
Figure 26-4. Dividers and PLL Blocks Diagram
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the
output of the corresponding divider and the PLL output is a continuous signal at level 0. On
reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0.
The PLL (PLLA, PLLB) allows multiplication of the divider’s outputs. The PLL clock signal has a
frequency that depends on the respective source signal frequency and on the parameters DIV
(DIVA, DIVB) and MUL (MULA, MULB). The factor applied to the source signal frequency is
(MUL + 1)/DIV. When MUL is written to 0, the PLL is disabled and its power consumption is
saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field.
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK (LOCKA,
LOCKB) bit in PMC_SR is automatically cleared. The values written in the PLLCOUNT field
(PLLACOUNT, PLLBCOUNT) in CKGR_PLLR (CKGR_PLLAR, CKGR_PLLBR) are loaded in
the PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it
MAINCK
shows the block diagram of the dividers and PLL blocks.
SLCK
Divider B
Divider A
DIVB
DIVA
MULB
MULA
PLLACOUNT
PLLBCOUNT
PLLADIV2
PLLBDIV2
Counter
Counter
PLL B
PLL A
PLL B
PLL A
OUTB
OUTA
LOCKB
LOCKA
SAM4S
SAM4S
PLLBCK
PLLACK
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