SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 58

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.4.2.3
Table 11-4.
58
58
Address Range
0x00000000 - 0x1FFFFFFF
0x20000000 - 0x3FFFFFFF
0x40000000 - 0x5FFFFFFF
0x60000000 - 0x9FFFFFFF
0xA0000000 - 0xDFFFFFFF
0xE0000000 - 0xE00FFFFF
0xE0100000 - 0xFFFFFFFF
Additional Memory Access Constraints For Shared Memory
SAM4S
SAM4S
Behavior of Memory Accesses
Memory Access Behavior
-
<
The behavior of accesses to each region in the memory map is:
Note:
The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends
that programs always use the Code region. This is because the processor has separate buses
that enable instruction fetches and data accesses to occur simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see
When a system includes shared memory, some memory regions have additional access con-
straints, and some regions are subdivided, as
Table 11-5.
Address Range
0x00000000-
0x1FFFFFFF
0x20000000-
0x3FFFFFFF
0x40000000-
0x5FFFFFFF
Memory Region
Code
SRAM
Peripheral
External RAM
External device
Private Peripheral Bus
Reserved
Means that the memory system does not guarantee the ordering of the accesses.
Means that accesses are observed in program order, that is, A1 is always observed
before A2.
1. See
Memory Region Shareability Policies
“Memory Regions, Types and Attributes”
“Memory Protection Unit (MPU)”
Memory Region
Code
SRAM
Peripheral
Memory
Type
Normal
Normal
Device
Normal
Device
Strongly-
ordered
Device
(1)
(1)
(1)
(1)
(1)
(1)
(1)
XN
-
-
XN
-
XN
XN
XN
Memory Type
Normal
Normal
Device
Description
Executable region for program code. Data can also be
put here.
Executable region for data. Code can also be put here.
This region includes bit band and bit band alias areas,
see
This region includes bit band and bit band alias areas,
see
Executable region for data.
External Device memory
This region includes the NVIC, System timer, and
system control block.
Reserved
Table 11-5
(1)
(1)
(1)
Table
Table
.
for more information.
11-6.
11-6.
shows:
Shareability
-
-
-
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
(2)
(2)

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