SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 96

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.6.4.3
96
96
SAM4S
SAM4S
LDR and STR, Register Offset
Load and Store with register offset.
Syntax
where:
op
type
cond
Rt
Rn
Rm
LSL #n
Operation
LDR instructions load a register with a value from memory.
STR instructions store a register value into memory.
The memory address to load from or store to is at an offset from the register Rn. The offset is
specified by the register Rm and can be shifted left by up to 3 bits using LSL.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and half-
words can either be signed or unsigned. See
Restrictions
In these instructions:
When Rt is PC in a word load instruction:
Condition Flags
• Rn must not be PC
• Rm must not be SP and must not be PC
• Rt can be SP only for word loads and word stores
• Rt can be PC only for word loads.
• bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this
• if the instruction is conditional, it must be the last instruction in the IT block.
halfword-aligned address
op{type}{cond} Rt, [Rn, Rm {, LSL #n}]
LDR
STR
B
SB
H
SH
-
is one of:
Load Register.
Store Register.
is one of:
unsigned byte, zero extend to 32 bits on loads.
signed byte, sign extend to 32 bits (LDR only).
unsigned halfword, zero extend to 32 bits on loads.
signed halfword, sign extend to 32 bits (LDR only).
omit, for word.
is an optional condition code, see
is the register to load or store.
is the register on which the memory address is based.
is a register containing a value to be used as the offset.
is an optional shift, with n in the range 0 to 3.
“Address Alignment”
“Conditional Execution”
.
.
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11

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