SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 371

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
21.4
Product Dependencies
21.4.1
Power Management
The CRCCU is clocked through the Power Management Controller (PMC), the programmer
must first configure the CRCCU in the PMC to enable the CRCCU clock.
21.4.2
Interrupt Source
The CRCCU has an interrupt line connected to the Interrupt Controller. Handling the CRCCU
interrupt requires programming the Interrupt Controller before configuring the CRCCU.
21.5
CRCCU Functional Description
21.5.1
CRC Calculation Unit description
The CRCCU integrates a dedicated Cyclic Redundancy Check (CRC) engine. When configured
and activated, this CRC engine performs a checksum computation on a Memory Area. CRC
computation is performed from the LSB to MSB bit. Three different polynomials are available
CCIT802.3, CASTAGNOLI and CCIT16, see the bitfield description,
mial” on page
21.5.2
CRC Calculation Unit Operation
The CRCCU has a DMA controller that supports programmable CRC memory checks. When
enabled, the DMA channel reads a programmable amount of data and computes CRC on the fly.
The CRCCU is controlled by two registers, TR_ADDR and TR_CTRL which need to be mapped
in the internal SRAM. The addresses of these two registers are pointed at by the
CRCCU_DSCR register.
Figure 21-2. CRCCU Descriptor Memory Mapping
TR_ADDR defines the start address of memory area targeted for CRC calculation.
TR_CTRL defines the buffer transfer size, the transfer width (byte, halfword, word) and the
transfer-completed interrupt enable.
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
387, for details.
CRCCU_DSCR+0x0
CRCCU_DSCR+0x4
CRCCU_DSCR+0x8
CRCCU_DSCR+0xC
CRCCU_DSCR+0x10
SAM4S
SAM4S
“PTYPE: Primitive Polyno-
SRAM
Memory
TR_ADDR
TR_CTRL
Reserved
Reserved
TR_CRC
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