SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 142

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
142
142
SAM4S
SAM4S
op{cond} RdLo, RdHi, Rn, Rm
op{XY}{cond} RdLo, RdHi, Rn, Rm
op{X}{cond} RdLo, RdHi, Rn, Rm
where:
op
cond
RdHi, RdLo
Rn, Rm
Operation
The
The
The non-specified halfwords of the source registers are ignored.
The
complement signed 16-bit integers. These instructions:
Restrictions
• Multiplies the two’s complement signed word values from
• Adds the 64-bit value in
• Writes the 64-bit result of the multiplication and addition in
• Multiplies the specified signed halfword, Top or Bottom, values from
• Adds the resulting sign-extended 32-bit product to the 64-bit value in
• Writes the 64-bit result of the multiplication and addition in
• if
• Or if
• Add the two multiplication results to the signed 64-bit value in
• Write the 64-bit product in
Rm
of
resulting 64-bit product.
SMLAL
SMLALBB
SMLALD
X
Rm
and the bottom signed halfword values of
is not present, multiply the top signed halfword value of
X
and the bottom signed halfword values of
is present, multiply the top signed halfword value of
instruction:
and
,
SMLALBT
is one of:
SMLAL Signed Multiply Accumulate Long
SMLAL Signed Multiply Accumulate Long (halfwords, X and Y)
X and Y specify which halfword of the source registers
and second multiply operand:
If
If
If
If
SMLALD Signed Multiply Accumulate Long Dual
SMLALDX Signed Multiply Accumulate Long Dual Reversed
If the
If
is an optional condition code, see
are the destination registers.
RdLo
For
the accumulating value.
are registers holding the first and second operands.
SMLALDX
X
X
Y
Y
X
is
is
is
is
is present, the multiplications are bottom × top and top × bottom.
SMLAL
is the lower 32 bits and
X
B
T
B
T
,
, then the top halfword, bits [31:16], of
, then the top halfword, bits [31:16], of
, then the bottom halfword, bits [15:0], of
, then the bottom halfword, bits [15:0], of
SMLALTB
is omitted, the multiplications are bottom × bottom and top × top.
,
instructions interpret the values from
SMLALBB
RdLo
RdLo
and
and
,
SMLALBT
SMLALTT
and
RdHi
RdHi
to the resulting 64-bit product.
,
RdHi
SMLALTB
instructions:
.
is the upper 32 bits of the 64-bit integer.
“Conditional Execution”
Rn
,
SMLALTT
Rn
with the bottom signed halfword of
with the top signed halfword of
Rn
Rm
,
Rn
Rm
is used.
SMLALD
is used.
Rn
Rn
is used.
is used.
RdLo
RdLo
Rn
Rn
and
with the bottom signed halfword
Rn
with the top signed halfword of
RdLo
and
and
and
and
and
.
Rm
and
SMLALDX,
Rm
.
RdHi
RdHi
Rm
Rn
RdLo
as four halfword two’s
and
RdHi
.
are used as the first
.
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
and
to create the
they also hold
Rm
RdHi
.
.
Rm
Rm
.
.

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