SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 865

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
35.11 HSMCI Boot Operation Mode
35.11.1
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Boot Procedure, Processor Mode
If STOP_TRANMISSION (CMD12) is successful, then the device is again ready for ATA com-
mands. However, if the error recovery procedure does not work as expected or there is another
timeout, the next step is to issue GO_IDLE_STATE (CMD0) to the device. GO_IDLE_STATE
(CMD0) is a hard reset to the device and completely resets all device states.
Note that after issuing GO_IDLE_STATE (CMD0), all device initialization needs to be completed
again. If the CE-ATA device completes all MMC commands correctly but fails the ATA command
with the ERR bit set in the ATA Status register, no error recovery action is required. The ATA
command itself failed implying that the device could not complete the action requested, how-
ever, there was no communication or protocol failure. After the device signals an error by setting
the ERR bit to one in the ATA Status register, the host may attempt to retry the command.
In boot operation mode, the processor can read boot data from the slave (MMC device) by keep-
ing the CMD line low after power-on before issuing CMD1. The data can be read from either the
boot area or user area, depending on register setting. As it is not possible to boot directly on SD-
CARD, a preliminary boot code must be stored in internal Flash.
• Issue STOP_TRANSMISSION (CMD12) and successfully receive the R1 response.
• Issue a software reset to the CE-ATA device using FAST_IO (CMD39).
1. Configure the HSMCI data bus width programming SDCBUS Field in the
2. Set the byte count to 512 bytes and the block count to the desired number of blocks,
3. Issue the Boot Operation Request command by writing to the HSMCI_CMDR register
4. The BOOT_ACK field located in the HSMCI_CMDR register must be set to one, if the
5. Host processor can copy boot data sequentially as soon as the RXRDY flag is
6. When Data transfer is completed, host processor shall terminate the boot stream by
HSMCI_SDCR register. The BOOT_BUS_WIDTH field located in the device Extended
CSD register must be set accordingly.
writing BLKLEN and BCNT fields of the HSMCI_BLKR Register.
with SPCMD field set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data
transfer”.
BOOT_ACK field of the MMC device located in the Extended CSD register is set to one.
asserted.
writing the HSMCI_CMDR register with SPCMD field set to BOOTEND.
SAM4S
SAM4S
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